void initMAC( const u8* bytMacAddress )
{
pdata = bytMacAddress;
// Initialize the SPI and the CS pin
theclock = platform_spi_setup( ENC28J60_SPI_ID, PLATFORM_SPI_MASTER, ENC28J60_SPI_CLOCK, 0, 0, 8 );
platform_pio_op( ENC28J60_CS_PORT, 1 << ENC28J60_CS_PIN, PLATFORM_IO_PIN_SET );
platform_pio_op( ENC28J60_CS_PORT, 1 << ENC28J60_CS_PIN, PLATFORM_IO_PIN_DIR_OUTPUT );
#if defined( ENC28J60_RESET_PORT ) && defined( ENC28J60_RESET_PIN )
platform_pio_op( ENC28J60_RESET_PORT, 1 << ENC28J60_RESET_PIN, PLATFORM_IO_PIN_CLEAR );
platform_pio_op( ENC28J60_RESET_PORT, 1 << ENC28J60_RESET_PIN, PLATFORM_IO_PIN_DIR_OUTPUT );
platform_timer_delay( 0, 30000 );
platform_pio_op( ENC28J60_RESET_PORT, 1 << ENC28J60_RESET_PIN, PLATFORM_IO_PIN_SET );
#endif
ResetMac(); // erm. Resets the MAC.
// setup memory by defining ERXST and ERXND
platform_timer_delay( 0, 20000 );
BankSel(0); // select bank 0
WriteCtrReg(ERXSTL,(u08)( RXSTART & 0x00ff));
WriteCtrReg(ERXSTH,(u08)((RXSTART & 0xff00)>> 8));
WriteCtrReg(ERXNDL,(u08)( RXEND & 0x00ff));
WriteCtrReg(ERXNDH,(u08)((RXEND & 0xff00)>>8));
// Make sure Rx Read ptr is at the start of Rx segment
WriteCtrReg(ERXRDPTL, (u08)( RXSTART & 0x00ff));
WriteCtrReg(ERXRDPTH, (u08)((RXSTART & 0xff00)>> 8));
BankSel(1); // select bank 1
WriteCtrReg(ERXFCON,( ERXFCON_UCEN + ERXFCON_CRCEN + ERXFCON_BCEN));
// Initialise the MAC registers
BankSel(2); // select bank 2
SetBitField(MACON1, MACON1_MARXEN); // Enable reception of frames
WriteCtrReg(MACLCON2, 63);
WriteCtrReg(MACON3, MACON3_FRMLNEN + // Type / len field will be checked
MACON3_TXCRCEN + // MAC will append valid CRC
MACON3_PADCFG0); // All small packets will be padded
SetBitField(MACON4, MACON4_DEFER);
WriteCtrReg(MAMXFLL, (u08)( MAXFRAMELEN & 0x00ff)); // set max frame len
WriteCtrReg(MAMXFLH, (u08)((MAXFRAMELEN & 0xff00)>>8));
WriteCtrReg(MABBIPG, 0x12); // back to back interpacket gap. set as per data sheet
WriteCtrReg(MAIPGL , 0x12); // non back to back interpacket gap. set as per data sheet
WriteCtrReg(MAIPGH , 0x0C);
//Program our MAC address
BankSel(3);
WriteCtrReg(MAADR1,bytMacAddress[0]);
WriteCtrReg(MAADR2,bytMacAddress[1]);
WriteCtrReg(MAADR3,bytMacAddress[2]);
WriteCtrReg(MAADR4,bytMacAddress[3]);
WriteCtrReg(MAADR5,bytMacAddress[4]);
WriteCtrReg(MAADR6,bytMacAddress[5]);
// Initialise the PHY registes
WritePhyReg(PHCON1, 0x00);
WritePhyReg(PHCON2, PHCON2_HDLDIS);
WriteCtrReg(ECON1, ECON1_RXEN); //Enable the chip for reception of packets
SetBitField(EIE, EIE_INTIE);
WritePhyReg(PHIE, PHIE_PGEIE|PHIE_PLNKIE);
ReadPhyReg(PHIR);
}
void initMAC(unsigned char* deviceMAC) {
/*Initialize the SPI Module*/
spiInit();
/*Execute a Soft Reset to the MAC*/
ResetMac();
/*Setup the 8kb Memory space on the ENC28J60
by defining ERXST and ERXND*/
BankSel(0);//Select Bank 0
WriteCtrReg(ERXSTL,(unsigned char)( RXSTART & 0x00ff));
WriteCtrReg(ERXSTH,(unsigned char)((RXSTART & 0xff00)>> 8));
WriteCtrReg(ERXNDL,(unsigned char)( RXEND & 0x00ff));
WriteCtrReg(ERXNDH,(unsigned char)((RXEND & 0xff00)>>8));
/*Set RX Read pointer to start of RX Buffer*/
WriteCtrReg(ERXRDPTL, (unsigned char)( RXSTART & 0x00ff));
WriteCtrReg(ERXRDPTH, (unsigned char)((RXSTART & 0xff00)>> 8));
/*Setup Transmit Buffer*/
WriteCtrReg(ETXSTL,(unsigned char)( TXSTART & 0x00ff));//Start of buffer
WriteCtrReg(ETXSTH,(unsigned char)((TXSTART & 0xff00)>>8));
/*End of buffer will depend on packets,so no point
hardcoding it*/
/*Set the RX Filters*/
BankSel(1);//Select Bank 1
/*REGISTER 8-1: ERXFCON: RECEIVE FILTER CONTROL REGISTER
See Page 50 of the datasheet.*/
WriteCtrReg(ERXFCON,( ERXFCON_UCEN + ERXFCON_CRCEN + ERXFCON_PMEN));
//---Setup packet filter---
//This part is taken from Guido Socher's AVR enc28j60 driver.Great Work,that.
//For broadcast packets we allow only ARP packtets
//All other packets should be unicast only for our mac (MAADR)
//The pattern to match on is therefore
//Type ETH.DST
//ARP BROADCAST
//06 08 -- ff ff ff ff ff ff -> ip checksum for theses bytes=f7f9
//in binary these poitions are:11 0000 0011 1111
//This is hex 303F->EPMM0=0x3f,EPMM1=0x30
WriteCtrReg(EPMM0, 0x3f);
WriteCtrReg(EPMM1, 0x30);
WriteCtrReg(EPMCSL,0x39);
WriteCtrReg(EPMCSH,0xf7);
/*Initialize the MAC Registers*/
BankSel(2); // select bank 2
SetBitField(MACON1, MACON1_MARXEN);// Enable reception of frames
WriteCtrReg(MACON3, MACON3_FRMLNEN + // Type / len field will be checked
MACON3_TXCRCEN + // MAC will append valid CRC
MACON3_PADCFG0); // All small packets will be padded
WriteCtrReg(MAMXFLL, (unsigned char)( MAXFRAMELEN & 0x00ff));// set max frame len
WriteCtrReg(MAMXFLH, (unsigned char)((MAXFRAMELEN & 0xff00)>>8));
WriteCtrReg(MABBIPG, 0x12);// back to back interpacket gap. set as per data sheet
WriteCtrReg(MAIPGL , 0x12);// non back to back interpacket gap. set as per data sheet
WriteCtrReg(MAIPGH , 0x0C);
/*Assign the MAC Address to the chip.*/
BankSel(3);//Select Bank 3.
WriteCtrReg(MAADR1,deviceMAC[0]);
WriteCtrReg(MAADR2,deviceMAC[1]);
WriteCtrReg(MAADR3,deviceMAC[2]);
WriteCtrReg(MAADR4,deviceMAC[3]);
WriteCtrReg(MAADR5,deviceMAC[4]);
WriteCtrReg(MAADR6,deviceMAC[5]);
/*Initialise the PHY registers
REGISTER 11-3: PHCON1: PHY CONTROL REGISTER 1
See Page 65 of the Datasheet.*/
WritePhyReg(PHCON1, 0x000);
/*
"If using half duplex, the host controller may wish to set
the PHCON2.HDLDIS bit to prevent automatic
loopback of the data which is transmitted."
See Section 6.6 on Page 40 */
WritePhyReg(PHCON2, PHCON2_HDLDIS);
/*Enable reception of packets*/
WriteCtrReg(ECON1, ECON1_RXEN);
}
