void vSetModPCM(PCM_MODULE ePcmModule, PCM_INFO_T *pPcmInfo)
{


    /// Mod PCM config
    if (ePcmModule == PCM_1)
    {
        /// clean
        WriteREG(PCM_INTF_CON, 0);

        vRegWriteBits(PCM_INTF_CON,  pPcmInfo->ePcmFmt,        PCM_FMT_POS, PCM_FMT_LEN);
        vRegWriteBits(PCM_INTF_CON,  pPcmInfo->ePcm8k16kmode,  PCM_MODE_POS, PCM_MODE_LEN);
        vRegWriteBits(PCM_INTF_CON,  pPcmInfo->ePcmWlen,       PCM_WLEN_POS, PCM_WLEN_LEN);
        vRegWriteBits(PCM_INTF_CON,  pPcmInfo->ePcmClkSrc,     PCM_SLAVE_POS, PCM_SLAVE_LEN);
        vRegWriteBits(PCM_INTF_CON,  pPcmInfo->ePcmBypassASRC, PCM_BYP_ASRC_POS, PCM_BYP_ASRC_LEN);
        vRegWriteBits(PCM_INTF_CON,  pPcmInfo->ePcmModemSel,   PCM_EXT_MODEM_POS, PCM_EXT_MODEM_LEN);
        vRegWriteBits(PCM_INTF_CON,  pPcmInfo->ePcmVbt16kSel,  PCM_VBT16K_MODE_POS, 1);
    }
    else
    {
        /// clean
        WriteREG(PCM_INTF_CON2, 0);

        vRegWriteBits(PCM_INTF_CON2, pPcmInfo->ePcmFmt,        PCM_FMT_POS, PCM_FMT_LEN);
        vRegWriteBits(PCM_INTF_CON2, pPcmInfo->ePcm8k16kmode,  PCM_MODE_POS, PCM_MODE_LEN);
        vRegWriteBits(PCM_INTF_CON2, pPcmInfo->ePcmWlen,       PCM_WLEN_POS, PCM_WLEN_LEN);
        vRegWriteBits(PCM_INTF_CON2, pPcmInfo->ePcmVbt16kSel,  12, 1);
    }
}
void vASRCEnable(bool bEnable)
{
    printk("[vASRCEnable]: bEnable = %x \n", bEnable);

    if ( bEnable == TRUE)
    {
        WriteREG(AFE_ASRC_CON6, 0x0001183F); //0x0001188F
        WriteREG(AFE_ASRC_CON0, 0x06003031);
    }
    else
    {
        WriteREG(AFE_ASRC_CON6, 0x00000000);
        WriteREG(AFE_ASRC_CON0, 0x06003030);
    }
}
// functions that could be commenly used
void vSetASRC(PCMMODE_T ePcm8k16kmode)
{
    printk("[vSetASRC]: PCMMODE_T = %x \n", ePcm8k16kmode);

    if ( ePcm8k16kmode == PCM_8K)
    {
        WriteREG(AFE_ASRC_CON1, 0x00001964);
        WriteREG(AFE_ASRC_CON2, 0x00400000);
        WriteREG(AFE_ASRC_CON3, 0x00400000);
        WriteREG(AFE_ASRC_CON4, 0x00001964);
        WriteREG(AFE_ASRC_CON7, 0x00000CB2);

    }
    else if ( ePcm8k16kmode == PCM_16K )
    {
        WriteREG(AFE_ASRC_CON1, 0x00000cb2);
        WriteREG(AFE_ASRC_CON2, 0x00400000);
        WriteREG(AFE_ASRC_CON3, 0x00400000);
        WriteREG(AFE_ASRC_CON4, 0x00000cb2);
        WriteREG(AFE_ASRC_CON7, 0x00000659);
    }
}
void vModPcmConfigAndRun(PCM_MODULE ePcmModule, PCM_INFO_T *pPcmInfo)
{
    MEMIF_CONFIG_T memModDaiCfg;
    SAMPLINGRATE_T eSampleRate;

    /// reset
    vStrongResetAFE();

    /// power on
    vAudioTopControl(); // AUDIO_TOP_CON0[14] = 1

    /// config FPGA
    WriteREG(FPGA_CFG0, 0x00000007);    // hopping 26m, MCLK : 3.072M
    if (ePcmModule == PCM_1 && pPcmInfo->ePcmModemSel == PCM_INT_MD)
    {
        vRegSetBit(FPGA_CFG1, 14);
    }

    /// get sample rate info
    eSampleRate = (pPcmInfo->ePcm8k16kmode == PCM_8K) ? AFE_8000HZ : AFE_16000HZ;

#if 1
    /// Sgen config as Tx data
    AFE_SINEGEN_INFO_T rSineTone;
    rSineTone.u4ch1_freq_div = 1;
    rSineTone.rch1_amp_div = SINE_TONE_1;
    rSineTone.rch1_sine_mode = eSampleRate;
    rSineTone.u4ch2_freq_div = 2;
    rSineTone.rch2_amp_div = SINE_TONE_1;
    rSineTone.rch2_sine_mode = eSampleRate;
    rSineTone.rloopback_mode = SINE_TONE_LOOPBACK_O7_O8; // O17_O18 simultaneously
    vAfeSineWaveGenCfg(&rSineTone);
#else
    bConnect(I05, O07, FALSE);
    bConnect(I06, O08, FALSE);

    MEMIF_CONFIG_T memDL1Cfg;
    memset(&memDL1Cfg, 0, sizeof(MEMIF_CONFIG_T));
    UINT32 addr;
    for(addr=u4DramVirBase; addr<=u4DramVirBase+0x3FFF; addr+=4)
    {
        *(UINT32*) addr = 0x66660000;
    }
    memDL1Cfg.eMemInterface = AFE_MEM_DL1;
    memDL1Cfg.eDaiModSamplingRate = eSampleRate;
    memDL1Cfg.eChannelConfig = AFE_STEREO;
    memDL1Cfg.rBufferSetting.u4AFE_MEMIF_BUF_BASE = u4DramPhyBase;
    memDL1Cfg.rBufferSetting.u4AFE_MEMIF_BUF_END = u4DramPhyBase + 0x3FFF;

    vAfeTurnOnMemif(&memDL1Cfg);

    /// Sgen config as Rx data
    AFE_SINEGEN_INFO_T rSineTone;
    rSineTone.u4ch1_freq_div = 1;
    rSineTone.rch1_amp_div = SINE_TONE_1;
    rSineTone.rch1_sine_mode = eSampleRate;
    rSineTone.u4ch2_freq_div = 0;
    rSineTone.rch2_amp_div = SINE_TONE_1;
    rSineTone.rch2_sine_mode = eSampleRate;
    rSineTone.rloopback_mode = SINE_TONE_LOOPBACK_O0_O1;
    vAfeSineWaveGenCfg(&rSineTone);

    vI2SSet(I2S_16BIT, I2S_I2S, eSampleRate, I2S_MASTER, I2S_OUT);
    vI2SEnable(I2S_ENABLE);

    vRegWriteBits(PCM_INTF_CON, 1,  26, 1);
#endif

    /// ASRC
    if (pPcmInfo->ePcmClkSrc==PCM_SLAVE && pPcmInfo->ePcmBypassASRC==PCM_GO_ASRC)
    {
        vSetASRC(pPcmInfo->ePcm8k16kmode);
        vASRCEnable(TRUE);
    }

    /// Config PCM
    vSetModPCM(ePcmModule, pPcmInfo);
    vModPCMEnable(ePcmModule, PCM_ENABLE);

    /// Memory Interface

    // Dump Rx data to MOD_DAI_Data (O_12)
    if (ePcmModule == PCM_1)
    {
        bConnect(I09, O012, false);
    }
    else
    {
        //bConnect(I14, O012, false);
        vRegSetBit(AFE_CONN4, 12);
    }

    // Memory (O_12)
    memset(&memModDaiCfg, 0, sizeof(MEMIF_CONFIG_T));
    memModDaiCfg.eMemInterface = AFE_MEM_MOD_PCM;
    memModDaiCfg.eDaiModSamplingRate = pPcmInfo->ePcm8k16kmode;
    memModDaiCfg.eDupWrite = AFE_DUP_WR_DISABLE;
    memModDaiCfg.rBufferSetting.u4AFE_MEMIF_BUF_BASE = MOD_PCM_BASE;
    memModDaiCfg.rBufferSetting.u4AFE_MEMIF_BUF_END = MOD_PCM_END;
    vAfeTurnOnMemif(&memModDaiCfg);
    vRegResetBit(AFE_DAC_CON0, MOD_PCM_ON);

#ifdef MOD_PCM_OFF_ON_TEST
    UINT32 u4PcmOffAddr = MOD_PCM_BASE + (MOD_PCM_SIZE / 4);
    UINT32 u4PcmOnAddr  = MOD_PCM_END  - (MOD_PCM_SIZE / 4) + 1;
    printk("MOD_PCM_OFF_ON_TEST: u4PcmOffAddr=0x%x, u4PcmOnAddr=0x%x\n", u4PcmOffAddr, u4PcmOnAddr);
#endif

    /// turn on
    vAfeTurnOn();
    vAfeSineWaveGenEnable(true);

    /// wait for 10 sec - observe frequency and amplitude
    vFpgaAudioClockDelaySec(10);

    /// wait
    vRegSetBit(AFE_DAC_CON0, MOD_PCM_ON);

#ifdef MOD_PCM_OFF_ON_TEST
    while( ReadREG(AFE_MOD_PCM_CUR) <= u4PcmOffAddr);
    vModPCMEnable(ePcmModule, PCM_DISABLE);

    while( ReadREG(AFE_MOD_PCM_CUR) <= u4PcmOnAddr);
    vModPCMEnable(ePcmModule, PCM_ENABLE);
#endif

    while( ReadREG(AFE_MOD_PCM_CUR) <= (ReadREG(AFE_MOD_PCM_END)-0x100));
    vRegResetBit(AFE_DAC_CON0, MOD_PCM_ON);


    /// turn off
    vAfeSineWaveGenEnable(false);

    vModPCMEnable(ePcmModule, PCM_DISABLE);
    vASRCEnable(FALSE);

    vRegResetBit(AFE_DAC_CON0, AFE_ON);

    /// wait for 10 sec - dump memory
    printk("Please config the next item\n");
    vFpgaAudioClockDelaySec(10);
}
/******************************************************************************
* Function      : vAudioHWGain1Test
* Description   : Test Case on HW gain1 function
* Parameter     :
* Return        : None
******************************************************************************/
BOOL vAudioHWGain1Test()
{
	BOOL ret = TRUE;

    MEMIF_CONFIG_T rAWBMemCfg,rDL1MemCfg;
	//need to change different sample rate to test
	SAMPLINGRATE_T srCnt = AFE_8000HZ;

	printk("[vAudioHWGain1Test] start\n");

	for(srCnt=AFE_8000HZ; srCnt<=AFE_48000HZ; srCnt++)	//could hard code to set specific sample rate
	{    
		memset(&rAWBMemCfg, 0, sizeof(MEMIF_CONFIG_T));
		memset(&rDL1MemCfg, 0, sizeof(MEMIF_CONFIG_T));
		// reset
		vStrongResetAFE();
		// power on
		vAudioTopControl();

		//set interconnection
		vRegSetBit(AFE_GAIN1_CONN, 16);	//I05 <-->O13	DL1_data in to HW GAIN1
		vRegSetBit(AFE_GAIN1_CONN, 21);	//I06 <-->O14
		
		vRegSetBit(AFE_GAIN1_CONN, 10);	//I11 <-->O04	HW GAIN1 output to I2S Out
		vRegSetBit(AFE_GAIN1_CONN, 8);	//I10 <-->O03
		
		vRegSetBit(AFE_GAIN1_CONN, 13);	//I11 <-->O06	HW GAIN1 to awb_data
		vRegSetBit(AFE_GAIN1_CONN, 12);	//I10 <-->O05

		//set HW GAIN and sample rate
		vRegWriteBits(AFE_GAIN1_CON0, u4SamplingRateConvert[srCnt], 4, 4);	//sample rate setting
		//WriteREG(AFE_GAIN1_CON1, 0x80000);	//define the target gain, default is 0x80000H which 0db
		vRegSetBit(AFE_GAIN1_CON0, 0);	//GAIN1 on


		// set I2S DAC output
   		vDACI2SSet(I2S_16BIT, I2S_I2S, srCnt, 0, I2S_NOSWAP);
	    vDACI2SEnable(I2S_ENABLE);

		//clear the SRAM and DRAM, modify the external DRAM size to 2M for test
		u4SramVirBuffer = u4SramVirBase;
	    u4SramPhyBuffer = u4SramPhyBase;
    	u4DramVirBuffer = u4DramVirBase;
	    u4DramPhyBuffer = u4DramPhyBase;
		printk("u4SramVirBuffer=0x%x, u4SramPhyBuffer=0x%x, u4DramVirBuffer=0x%x, u4DramPhyBuffer=0x%x\n",u4SramVirBuffer,u4SramPhyBuffer,u4DramVirBuffer,u4DramPhyBuffer);
	
		memset((void*)u4SramVirBuffer,0,AFE_INTERNAL_SRAM_SIZE);
		memset((void*)u4DramVirBuffer,0,AFE_EXTERNAL_DRAM_SIZE);	//need to set the DRAM size as (0x00200000) //2M to prepare enough buffer to dump PCM data
	
		unsigned int addr;
		unsigned int cnt = 0;
		unsigned int val = 0;

		//fill in source data
		for(addr=u4SramVirBuffer; addr<u4SramVirBuffer+AFE_INTERNAL_SRAM_SIZE-1; addr+=4)
		{
			*( unsigned int *)addr = table_sgen_golden_values_1[cnt++];
			if (cnt == 64)
				cnt = 0;
		}

	
		//AWB memory interface setting, use the DRAM, for record the data after HW gain1 control
		rAWBMemCfg.rBufferSetting.u4AFE_MEMIF_BUF_BASE = u4DramPhyBuffer;
		rAWBMemCfg.rBufferSetting.u4AFE_MEMIF_BUF_END= u4DramPhyBuffer+AFE_EXTERNAL_DRAM_SIZE-1;
		rAWBMemCfg.rBufferSetting.u4AFE_MEMIF_BUF_RP= rAWBMemCfg.rBufferSetting.u4AFE_MEMIF_BUF_BASE;
		rAWBMemCfg.rBufferSetting.u4AFE_MEMIF_BUF_WP= rAWBMemCfg.rBufferSetting.u4AFE_MEMIF_BUF_BASE;
		rAWBMemCfg.eChannelConfig = AFE_STEREO;
		rAWBMemCfg.eDupWrite = 0;
		rAWBMemCfg.eSamplingRate = srCnt;
		rAWBMemCfg.eMemInterface = AFE_MEM_AWB;
	

		// DL1 memory interface setting, use the internal SRAM, for output source data
		rDL1MemCfg.rBufferSetting.u4AFE_MEMIF_BUF_BASE = u4SramPhyBuffer;
		rDL1MemCfg.rBufferSetting.u4AFE_MEMIF_BUF_END= u4SramPhyBuffer+AFE_INTERNAL_SRAM_SIZE-1;
		rDL1MemCfg.rBufferSetting.u4AFE_MEMIF_BUF_RP= rDL1MemCfg.rBufferSetting.u4AFE_MEMIF_BUF_BASE;
		rDL1MemCfg.rBufferSetting.u4AFE_MEMIF_BUF_WP= rDL1MemCfg.rBufferSetting.u4AFE_MEMIF_BUF_BASE;
		rDL1MemCfg.eChannelConfig = AFE_STEREO;
		rDL1MemCfg.eDupWrite = 0;
		rDL1MemCfg.eSamplingRate = srCnt;
		rDL1MemCfg.eMemInterface = AFE_MEM_DL1;

		vAfeTurnOnMemif(&rAWBMemCfg);
		vAfeTurnOnMemif(&rDL1MemCfg);

		vAfeTurnOn();

		printk("[vAudioHWGain1Test] start to test\n");

		BOOL bBufferEnd = FALSE;
		BOOL bDirectUpdateTargetGain = FALSE;
		int i,j;
		int GDStepCnt,GUStepCnt;
	

		for(GDStepCnt=0; GDStepCnt<3; GDStepCnt++)	//set for Gain down step
		{
			WriteREG(AFE_GAIN1_CON2,uGainDownStep1[GDStepCnt]);	//GDStepCnt=0 is default value, set the gain down step value
		
			for(GUStepCnt=0; GUStepCnt<3; GUStepCnt++)	//set for Gain up step
			{
				WriteREG(AFE_GAIN1_CON3,uGainUpStep1[GUStepCnt]);	//set the gain up step value

				printk("uGainDownStep1=0x%x, uGainUpStep1=0x%x!!!\n",ReadREG(AFE_GAIN1_CON2),ReadREG(AFE_GAIN1_CON3));
			
				for(i=0; i<TestCount; i++)
				{
					if(bBufferEnd)
					{
						printk("[vAudioHWGain1Test] Buffer is runout of, stop1\n");
						break;
					}		
		
					vRegWriteBits(AFE_GAIN1_CON0, uSamplePerStep1[i], 8, 8);	//sample per step change

					printk("target gain before set, AFE_GAIN1_CON1=0x%x, AFE_GAIN1_CON0=0x%x!!!\n",ReadREG(AFE_GAIN1_CON1),ReadREG(AFE_GAIN1_CON0));

					for(j=0; j<TestCount; j++)	//set the target gain
					{
						WriteREG(AFE_GAIN1_CON1,uTargetGain1[j]);
						int Cnt = 0;
						bDirectUpdateTargetGain = FALSE;
						if(bBufferEnd) 
						{
							printk("[TcHWGain1Test] Buffer is runout of, stop2\n");
							break;
						}
						if(ReadREG(AFE_AWB_CUR) <= ReadREG(AFE_AWB_END) - 0x200)
						{
							printk("target gain set, AFE_GAIN1_CUR=0x%x, AFE_GAIN1_CON1=0x%x!!!\n",ReadREG(AFE_GAIN1_CUR),ReadREG(AFE_GAIN1_CON1));

							while(ReadREG(AFE_GAIN1_CUR)!= uTargetGain1[j])
							{
								vFpgaAudioClockDelaymSec(100);
								//could check the target gain changed before the current gain reach the target gain
	/*							if(Cnt++>=50)
								{
									printk("can't not reach the TargetGain in Time, update new target gain directly AFE_GAIN1_CUR=0x%x!!!\n",ReadREG(AFE_GAIN1_CUR));
									bDirectUpdateTargetGain = TRUE;
									break;
								}
	*/							//printk("AFE_GAIN1_CUR=0x%x!!!\n",ReadREG(AFE_GAIN1_CUR));
							}
							printk("current gain, AFE_GAIN1_CUR=0x%x!!!\n",ReadREG(AFE_GAIN1_CUR));
							if(!bDirectUpdateTargetGain)
								vFpgaAudioClockDelaySec(1);
						}
						else
						{
							bBufferEnd = TRUE;
							printk("[vAudioHWGain1Test] Buffer is runout of, stop3\n");
							break;
						}
					}//target gain change

					//set the breakpoint to check
					//ReadREG(FPGA_VERSION);	
					//ReadREG(FPGA_AUDIO_CLOCK);
				}			//sample per step change
			}
		}

		printk("AWB current address =0x%x!!!\n",ReadREG(AFE_AWB_CUR));
		printk("u4SramVirBuffer=0x%x, u4SramPhyBuffer=0x%x, u4DramVirBuffer=0x%x, u4DramPhyBuffer=0x%x\n",u4SramVirBuffer,u4SramPhyBuffer,u4DramVirBuffer,u4DramPhyBuffer);

    	vRegResetBit(AFE_DAC_CON0, AFE_ON);	//Stop
		//set the breakpoint to check
		ReadREG(FPGA_VERSION);	
		ReadREG(FPGA_AUDIO_CLOCK);
 
	} 	
    printk("[TcHWGain1Test] end\n");

	return ret;
}
/******************************************************************************
* Function      : vAudioHWGain2Test
* Description   : Test Case on HW gain2 function
* Parameter     :
* Return        : None
******************************************************************************/
BOOL vAudioHWGain2Test()
{
	BOOL ret = TRUE;

    MEMIF_CONFIG_T rAWBMemCfg;
	SAMPLINGRATE_T srCnt = AFE_8000HZ;

//	for(srCnt=AFE_8000HZ; srCnt<=AFE_48000HZ; srCnt++)	//could set the specific sample rate, need to meet the AudioPrecision
	{
    	printk("vAudioHWGain2Test start, srCnt=%d\n",srCnt);
		memset(&rAWBMemCfg, 0, sizeof(MEMIF_CONFIG_T));

		// reset
		vStrongResetAFE();
		// power on
		vAudioTopControl();

		//set interconnection
		vRegSetBit(AFE_GAIN2_CONN, 16);	//I00 <-->O15	I2S in to HW GAIN2
		vRegSetBit(AFE_GAIN2_CONN, 23);	//I01 <-->O16
		
		vRegSetBit(AFE_GAIN2_CONN, 10);	//I13 <-->O04	HW GAIN2 output to I2S Out
		vRegSetBit(AFE_GAIN2_CONN, 8);	//I12 <-->O03
	
		vRegSetBit(AFE_GAIN2_CONN, 13);	//I13 <-->O06	HW GAIN2 to awb
		vRegSetBit(AFE_GAIN2_CONN, 12);	//I12 <-->O05

		//set HW GAIN
		vRegWriteBits(AFE_GAIN2_CON0, u4SamplingRateConvert[srCnt], 4, 4);	//sample rate setting
		//WriteREG(AFE_GAIN2_CON2, 0x80000);	//define the target gain, default is 0x80000H which 0db
		vRegSetBit(AFE_GAIN2_CON0, 0);	//GAIN2 on

		// setup I2S in as slave mode
		vI2SSet(I2S_16BIT, I2S_I2S, srCnt, I2S_SLAVE, I2S_IN);
		vI2SEnable(I2S_ENABLE);
		vFOCEnable(TRUE);
	
		// set I2S DAC output
		vDACI2SSet(I2S_16BIT, I2S_I2S, srCnt, 0, I2S_NOSWAP);
		vDACI2SEnable(I2S_ENABLE);
		
		//clear the SRAM and DRAM
		//need to set the DRAM size as (0x00200000) //2M to prepare enough buffer to dump PCM data
		u4SramVirBuffer = u4SramVirBase;
	    u4SramPhyBuffer = u4SramPhyBase;
    	u4DramVirBuffer = u4DramVirBase;
	    u4DramPhyBuffer = u4DramPhyBase;

		printk("u4SramVirBuffer=0x%x, u4SramPhyBuffer=0x%x, u4DramVirBuffer=0x%x, u4DramPhyBuffer=0x%x\n",u4SramVirBuffer,u4SramPhyBuffer,u4DramVirBuffer,u4DramPhyBuffer);
		memset((void*)u4DramVirBuffer,0,AFE_EXTERNAL_DRAM_SIZE);	
		
		//AWB memory interface setting, use the DRAM
		rAWBMemCfg.rBufferSetting.u4AFE_MEMIF_BUF_BASE = u4DramPhyBuffer;
		rAWBMemCfg.rBufferSetting.u4AFE_MEMIF_BUF_END= u4DramPhyBuffer + AFE_EXTERNAL_DRAM_SIZE-1;
		rAWBMemCfg.rBufferSetting.u4AFE_MEMIF_BUF_RP= rAWBMemCfg.rBufferSetting.u4AFE_MEMIF_BUF_BASE;
		rAWBMemCfg.rBufferSetting.u4AFE_MEMIF_BUF_WP= rAWBMemCfg.rBufferSetting.u4AFE_MEMIF_BUF_BASE;
		rAWBMemCfg.eChannelConfig = AFE_STEREO;
		rAWBMemCfg.eDupWrite = 0;
		rAWBMemCfg.eSamplingRate = srCnt;
		rAWBMemCfg.eMemInterface = AFE_MEM_AWB;	


		vAfeTurnOnMemif(&rAWBMemCfg);

		vAfeTurnOn();
	

		BOOL bBufferEnd = FALSE;
		BOOL bDirectUpdateTargetGain = FALSE;
		int i,j;
		int GDStepCnt,GUStepCnt;
	
		//while(1)
		{
			for(GDStepCnt=0; GDStepCnt<3; GDStepCnt++)	//modify gain down step
			{
				WriteREG(AFE_GAIN2_CON2,uGainDownStep1[GDStepCnt]);	//GDStepCnt=0 is default value, set the gain down step value
		
				for(GUStepCnt=0; GUStepCnt<3; GUStepCnt++)	//modify gain up step
				{
					WriteREG(AFE_GAIN2_CON3,uGainUpStep1[GUStepCnt]);	//set the gain up step value

					printk("uGainDownStep2=0x%x, uGainUpStep2=0x%x!!!\n",ReadREG(AFE_GAIN2_CON2),ReadREG(AFE_GAIN2_CON3));
			
					for(i=0; i<TestCount; i++)
					{
						if(bBufferEnd)
						{
							printk("[vAudioHWGain2Test] Buffer is runout of, stop1\n");
							break;
						}				
						vRegWriteBits(AFE_GAIN2_CON0, uSamplePerStep1[i], 8, 8);	//sample per step change

						printk("target gain before set, AFE_GAIN2_CON1=0x%x, AFE_GAIN2_CON0=0x%x!!!\n",ReadREG(AFE_GAIN2_CON1),ReadREG(AFE_GAIN2_CON0));

						for(j=0; j<TestCount; j++)
						{
							WriteREG(AFE_GAIN2_CON1,uTargetGain1[j]);
							int Cnt = 0;
							bDirectUpdateTargetGain = FALSE;
							if(bBufferEnd) 
							{
								printk("[vAudioHWGain2Test] Buffer is runout of, stop2\n");
								break;
							}
							
							if(ReadREG(AFE_AWB_CUR) <= ReadREG(AFE_AWB_END) - 0x200)
							{
								printk("target gain set, AFE_GAIN2_CUR=0x%x, AFE_GAIN2_CON1=0x%x!!!\n",ReadREG(AFE_GAIN2_CUR),ReadREG(AFE_GAIN2_CON1));

								while(ReadREG(AFE_GAIN2_CUR)!= uTargetGain1[j])
								{
									vFpgaAudioClockDelaymSec(10);
		/*							if(Cnt++>=50)
									{
										printk("can't not reach the TargetGain in Time, update new target gain directly AFE_GAIN1_CUR=0x%x!!!\n",ReadREG(AFE_GAIN2_CUR));
										bDirectUpdateTargetGain = TRUE;
										break;
									}
	*/								//printk("AFE_GAIN2_CUR=0x%x!!!\n",ReadREG(AFE_GAIN2_CUR));
								}
							
								printk("current gain, AFE_GAIN2_CUR=0x%x!!!\n",ReadREG(AFE_GAIN2_CUR));
							
								if(!bDirectUpdateTargetGain)
									vFpgaAudioClockDelaySec(1);
							}				
							else
							{
								bBufferEnd = TRUE;
								printk("[vAudioHWGain2Test] Buffer is runout of, stop3\n");
								break;
							}
						}

						//while(1);	//do loop to check AudioPrecision input
						//set the breakpoint to check
						ReadREG(FPGA_VERSION);	
						ReadREG(FPGA_AUDIO_CLOCK);
					}			
				}
			}
		}
		printk("AWB current address =0x%x!!!\n",ReadREG(AFE_AWB_CUR));

	    vRegResetBit(AFE_DAC_CON0, AFE_ON);	//Stop
    	ReadREG(FPGA_VERSION);
		ReadREG(FPGA_AUDIO_CLOCK);
	}
 
	printk("vAudioHWGain2Test end\n");

	return ret;

}
void ApAudSys_config(void)
{
	
#if defined(IC_MODULE_TEST)
	// For SLT test, these register settings would affect the AFE test case.
#else   // Normal usage, IC_MODULE_TEST

#if defined(MT6589)
	// for second modem with slave mode
	// vSetASRC
	// WriteREG(AFE_ASRC_CON1, 0x00000cb2);
	// WriteREG(AFE_ASRC_CON2, 0x00400000);
	// WriteREG(AFE_ASRC_CON3, 0x00400000);
	// WriteREG(AFE_ASRC_CON4, 0x00000cb2);
	// WriteREG(AFE_ASRC_CON7, 0x00000659);
	
	// vASRCEnable
	// WriteREG(AFE_ASRC_CON6, 0x00000000);
	// WriteREG(AFE_ASRC_CON0, 0x06003030);

	// MAIN setting for interconnection
	WriteREG(AUDIO_TOP_CON0, 0x00004000);
	WriteREG(AFE_TOP_CON0, 0x00000000);
	WriteREG(AFE_DAC_CON0, 0x00000001);
	WriteREG(AFE_CONN1, 0x02000000); // MD2
	WriteREG(AFE_CONN2, 0x24000200); // MD2	
	WriteREG(AFE_CONN3, 0x08000000); // MD1
	WriteREG(AFE_CONN4, 0x00012001); // MD1

	// sidetone
	WriteREG(AFE_SIDDETONE_CON1, 0x00000000);
	

	// MD2
	WriteREG(PCM_INTF_CON1, 0x0000006F);
	// WriteREG(PCM_INTF_CON2, 0x00000000);
	// MD1
	WriteREG(PCM_INTF_CON, 0x0000000F);

	// i2s to external dac
	WriteREG(AFE_I2S_CON1, 0x00000409); //dac 16k
	WriteREG(AFE_I2S_CON2, 0x00000409); //adc 16k


#elif defined(MT6572) || defined(MT6582) || defined(MT6592) || defined(MT6571)


	WriteREG(AUDIO_TOP_CON0, 0x60004000);
	WriteREG(AFE_TOP_CON0, 0x00000000);
	
	// MAIN setting for interconnection
	WriteREG(AFE_CONN3, 0x08000000); // MD1, i14->o3
	WriteREG(AFE_CONN4, 0x00012001); // MD1, i4->o18, i3->o17, i14->o4

	// sidetone
	WriteREG(AFE_SIDDETONE_CON1, 0x00000000);

	// MD1
	WriteREG(PCM_INTF_CON, 0x0000000F); 

	// new interface with SRC	
	WriteREG(AFE_ADDA_NEWIF_CFG0, 0x03F87201);
	WriteREG(AFE_ADDA_NEWIF_CFG1, 0x03117580);

	WriteREG(AFE_ADDA_DL_SRC2_CON0, 0x33001823); // DL 16k : 0x33001823, DL 8k : 0x03001823
	WriteREG(AFE_ADDA_DL_SRC2_CON1, 0xFFFF0000);
		
	WriteREG(AFE_ADDA_UL_SRC_CON0, 0x000A0001); // UL 16k : 0x000A0001, UL 8k : 0x00000001
	WriteREG(AFE_ADDA_UL_SRC_CON1, 0x00000000);
	
	WriteREG(AFE_ADDA_TOP_CON0, 0x00000000);
	WriteREG(AFE_I2S_CON1, 0x0000040B); //I2S out, 要和ADDA一起開,位置在0x0034
	WriteREG(AFE_ADDA_UL_DL_CON0, 0x00000001);
	WriteREG(AFE_DAC_CON0, 0x00000001); // keep in last, confirm by Andrew

	// PMIC_AudioConfig(); 
	PMIC_AudioConfig_Loopback();
	
#endif // chip base define

#endif  // IC_MODULE_TEST

	
}
// void l1sp_configApAfeHwForBt(void)
void ApAudSys_config_forBt(void)
{
#if defined(MT6589)

	// GPIO set to external
	/*
	WriteREG(0xA00050D0, 0x5000 ); // GPIO_DIR13 
	WriteREG(0xA00050E0, 0x0001 ); // GPIO_DIR14
	WriteREG(0xA0005EC0, 0x1248 ); // GPIO_MODE2C, 
	*/
	
	// MAIN setting for interconnection
	WriteREG(AUDIO_TOP_CON0, 0x00004000);
	WriteREG(AFE_TOP_CON0, 0x00000000);
	WriteREG(AFE_DAC_CON0, 0x00000001);

	WriteREG(AFE_CONN1, 0x00000000); 
	WriteREG(AFE_CONN2, 0x00000000); 	
	WriteREG(AFE_CONN3, 0x00400000); // i14, o2 
	WriteREG(AFE_CONN4, 0x00000000); 

	WriteREG(AFE_GAIN2_CON0, 0x0000c801);
	WriteREG(AFE_GAIN2_CON, 0x01040000); // MD1
	WriteREG(AFE_GAIN2_CON2, 0x000000C0);

	
	WriteREG(AFE_DAIBT_CON0, 0x105F);
	WriteREG(AFE_MRGIF_CON, 0x00900001);
	
	// MD2
	WriteREG(PCM_INTF_CON1, 0x0000006F);
	// WriteREG(PCM_INTF_CON2, 0x00000000);
	// MD1
	WriteREG(PCM_INTF_CON, 0x0000000F);
#elif defined(MT6572)
// TODO:
#elif defined(MT6582)
// TODO:
#endif
}