/** * * This function sets the input/output frame size in Active Size register and * enables the register update. * * @param InstancePtr is a pointer to the Xccm instance. * * @return None. * * @note None. * ******************************************************************************/ void XCcm_Setup(XCcm *InstancePtr) { u32 Data; /* Verify arguments. */ Xil_AssertVoid(InstancePtr != NULL); XCcm_RegUpdateDisable(InstancePtr); /* Write into active size register */ Data = ((((InstancePtr->VSize)) << (u32)(XCCM_ACTSIZE_NUM_LINE_SHIFT)) & (XCCM_ACTSIZE_NUM_LINE_MASK)) | (((InstancePtr->HSize)) & (u32)(XCCM_ACTSIZE_NUM_PIXEL_MASK)); XCcm_WriteReg(InstancePtr->Config.BaseAddress, (XCCM_ACTIVE_SIZE_OFFSET), Data); XCcm_RegUpdateEnable(InstancePtr); }
void avnet_config_vgap60_video(demo_t *pInstance) { int status; Xil_Out32(XPAR_TCM_RECEIVER_0_S00_AXI_BASEADDR + 0x0000, 0x0001); XCfa_Reset(pInstance->pcfa); XCcm_Reset(pInstance->pccm); XRgb2YCrCb_Reset(pInstance->prgb2ycrcb); XCresample_Reset(pInstance->pcresample); XAxiVdma_Reset(pInstance->paxivdma, XAXIVDMA_WRITE); XAxiVdma_Reset(pInstance->paxivdma, XAXIVDMA_READ); XVtc_Reset(pInstance->pvtc); XOSD_Reset(pInstance->posd); /* CLKWIZ */ Xil_Out32(XPAR_CLK_WIZ_1_BASEADDR + 0x0200, 0x00002203); Xil_Out32(XPAR_CLK_WIZ_1_BASEADDR + 0x0208, 0x0000002D); Xil_Out32(XPAR_CLK_WIZ_1_BASEADDR + 0x025C, 0x00000007); Xil_Out32(XPAR_CLK_WIZ_1_BASEADDR + 0x025C, 0x00000002); status = 0; while (!status) { status = Xil_In32(XPAR_CLK_WIZ_1_BASEADDR + 0x0004); } /* ISERDES Reset Assert */ Xil_Out32(XPAR_TCM_RECEIVER_0_S00_AXI_BASEADDR + 0x0000, 0x0001); /* TCM Initialization */ tca9548_i2c_mux_select(pInstance->piicps, EMBV_IIC_MUX_CAM); // tcm5117pl_get_chip_id(pInstance->piicps); tcm5117pl_init(pInstance->piicps, TCM5117PL_VGAP60); /* CFA */ XCfa_Reset(pInstance->pcfa); XCfa_Enable(pInstance->pcfa); XCfa_SetBayerPhase(pInstance->pcfa, 0x00000001); XCfa_SetActiveSize(pInstance->pcfa, 656, 496); XCfa_RegUpdateEnable(pInstance->pcfa); /* CCM */ XCcm_Reset(pInstance->pccm); XCcm_Enable(pInstance->pccm); XCcm_SetCoefMatrix(pInstance->pccm, &CCM_IDENTITY); XCcm_SetRgbOffset(pInstance->pccm, 0, 0, 0); XCcm_SetActiveSize(pInstance->pccm, 656, 496); XCcm_RegUpdateEnable(pInstance->pccm); /* RGB2YCRCB */ XRgb2YCrCb_Reset(pInstance->prgb2ycrcb); XRgb2YCrCb_Enable(pInstance->prgb2ycrcb); XRgb2YCrCb_Configuration(pInstance->prgb2ycrcb, XRGB_STANDARD_ITU_601_SD, XRGB_TV_16_TO_240, XRGB_DATA_WIDTH_10); XRgb2YCrCb_SetActiveSize(pInstance->prgb2ycrcb, 656, 496); XRgb2YCrCb_RegUpdateEnable(pInstance->prgb2ycrcb); /* CRESAMPLE */ XCresample_Reset(pInstance->pcresample); XCresample_Enable(pInstance->pcresample); XCresample_Configuration(pInstance->pcresample); XCresample_SetActiveSize(pInstance->pcresample, 656, 496); XCresample_RegUpdateEnable(pInstance->pcresample); /* AXIVDMA */ XAxiVdma_Reset(pInstance->paxivdma, XAXIVDMA_WRITE); XAxiVdma_Reset(pInstance->paxivdma, XAXIVDMA_READ); ReadSetup(pInstance->paxivdma, 0x30000000, 2, 0, 1, 1, 0, 0, 656, 496, 2048, 2048); WriteSetup(pInstance->paxivdma, 0x30000000, 2, 0, 1, 1, 0, 0, 656, 496, 2048, 2048); StartTransfer(pInstance->paxivdma); /* VTC */ XVtc_Timing Timing; XVtc_Reset(pInstance->pvtc); XVtc_RegUpdateEnable(pInstance->pvtc); XVtc_Enable(pInstance->pvtc); XVtc_ConvVideoMode2Timing(pInstance->pvtc, XVTC_VMODE_VGA, &Timing); Timing.HSyncPolarity = 1; Timing.VSyncPolarity = 1; XVtc_SetGeneratorTiming(pInstance->pvtc, &Timing); /* OSD */ XOSD_Reset(pInstance->posd); XOSD_RegUpdateEnable(pInstance->posd); XOSD_Enable(pInstance->posd); XOSD_SetScreenSize(pInstance->posd, 656, 496); XOSD_SetBackgroundColor(pInstance->posd, 0x80, 0x80, 0x80); // Layer 0 - Test Pattern Generator XOSD_SetLayerPriority(pInstance->posd, 0, XOSD_LAYER_PRIORITY_0); XOSD_SetLayerAlpha(pInstance->posd, 0, 1, 0xFF); XOSD_SetLayerDimension(pInstance->posd, 0, 0, 0, 656, 496); XOSD_EnableLayer(pInstance->posd, 0); // ISERDES Reset De-Assert Xil_Out32(XPAR_TCM_RECEIVER_0_S00_AXI_BASEADDR + 0x0000, 0x0000); }