/** * * Read the flash in Linear QSPI mode. * * @param InstancePtr is a pointer to the XQspiPs instance. * @param RecvBufPtr is a pointer to a buffer for received data. * @param Address is the starting address within the flash from * from where data needs to be read. * @param ByteCount contains the number of bytes to receive. * * @return * - XST_SUCCESS if read is performed * - XST_FAILURE if Linear mode is not set * * @note None. * * ******************************************************************************/ int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr, u32 Address, unsigned ByteCount) { Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(RecvBufPtr != NULL); Xil_AssertNonvoid(ByteCount > 0); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); #ifndef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR #define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000 #endif /* * Enable the controller */ XQspiPs_Enable(InstancePtr); if (XQspiPs_GetLqspiConfigReg(InstancePtr) & XQSPIPS_LQSPI_CR_LINEAR_MASK) { memcpy((void*)RecvBufPtr, (const void*)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR + Address), (size_t)ByteCount); return XST_SUCCESS; } else { return XST_FAILURE; } /* * Disable the controller */ XQspiPs_Disable(InstancePtr); }
/** * * Aborts a transfer in progress by disabling the device and flush the RxFIFO. * The byte counts are cleared, the busy flag is cleared. * * @param InstancePtr is a pointer to the XQspiPs instance. * * @return None. * * @note * * This function does a read/modify/write of the config register. The user of * this function needs to take care of critical sections. * ******************************************************************************/ void XQspiPs_Abort(XQspiPs *InstancePtr) { u32 ConfigReg; u32 IsLock; XQspiPs_Disable(InstancePtr); /* * De-assert slave select lines. */ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET); ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK); XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); /* * QSPI Software Reset */ IsLock = XQspiPs_ReadReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCKSTA); if (IsLock) { XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_UNLOCK, SLCR_UNLOCK_MASK); } XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, LQSPI_RST_CTRL_MASK); XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, 0x0); if (IsLock) { XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCK, SLCR_LOCK_MASK); } /* * Set the RX and TX FIFO threshold to reset value (one) */ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE); InstancePtr->RemainingBytes = 0; InstancePtr->RequestedBytes = 0; InstancePtr->IsBusy = FALSE; }
/** * * Aborts a transfer in progress by disabling the device and flush the RxFIFO. * The byte counts are cleared, the busy flag is cleared. * * @param InstancePtr is a pointer to the XQspiPs instance. * * @return None. * * @note * * This function does a read/modify/write of the config register. The user of * this function needs to take care of critical sections. * ******************************************************************************/ void XQspiPs_Abort(XQspiPs *InstancePtr) { u32 ConfigReg; XQspiPs_Disable(InstancePtr); /* * De-assert slave select lines. */ ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET); ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK); XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); /* * Set the RX and TX FIFO threshold to reset value (one) */ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE); /* * Clear the RX FIFO and drop any data. */ while ((XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET) & XQSPIPS_IXR_RXNEMPTY_MASK) != 0) { XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPS_RXD_OFFSET); } InstancePtr->RemainingBytes = 0; InstancePtr->RequestedBytes = 0; InstancePtr->IsBusy = FALSE; }
/** * Transfers specified data on the QSPI bus in polled mode. * * The caller has the option of providing two different buffers for send and * receive, or one buffer for both send and receive, or no buffer for receive. * The receive buffer must be at least as big as the send buffer to prevent * unwanted memory writes. This implies that the byte count passed in as an * argument must be the smaller of the two buffers if they differ in size. * Here are some sample usages: * <pre> * XQspiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount) * The caller wishes to send and receive, and provides two different * buffers for send and receive. * * XQspiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount) * The caller wishes only to send and does not care about the received * data. The driver ignores the received data in this case. * * XQspiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount) * The caller wishes to send and receive, but provides the same buffer * for doing both. The driver sends the data and overwrites the send * buffer with received data as it transfers the data. * * XQspiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount) * The caller wishes to only receive and does not care about sending * data. In this case, the caller must still provide a send buffer, but * it can be the same as the receive buffer if the caller does not care * what it sends. The device must send N bytes of data if it wishes to * receive N bytes of data. * * </pre> * * @param InstancePtr is a pointer to the XQspiPs instance. * @param SendBufPtr is a pointer to a data buffer that needs to be * transmitted. This buffer must not be NULL. * @param RecvBufPtr is a pointer to a buffer for received data. * This argument can be NULL if do not care about receiving. * @param ByteCount contains the number of bytes to send/receive. * The number of bytes received always equals the number of bytes * sent. * @return * - XST_SUCCESS if the buffers are successfully handed off to the * device for transfer. * - XST_DEVICE_BUSY indicates that a data transfer is already in * progress. This is determined by the driver. * * @note * * This function is not thread-safe. The higher layer software must ensure that * no two threads are transferring data on the QSPI bus at the same time. * ******************************************************************************/ int XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, unsigned ByteCount) { u32 StatusReg; u32 ConfigReg; u8 Instruction; u32 Data; u8 TransCount; unsigned int Index; XQspiPsInstFormat *CurrInst; XQspiPsInstFormat NewInst[2]; u8 SwitchFlag = 0; u8 IsManualStart = FALSE; u32 RxCount = 0; CurrInst = &NewInst[0]; /* * The RecvBufPtr argument can be NULL. */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(SendBufPtr != NULL); Xil_AssertNonvoid(ByteCount > 0); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); /* * Check whether there is another transfer in progress. Not thread-safe. */ if (InstancePtr->IsBusy) { return XST_DEVICE_BUSY; } /* * Set the busy flag, which will be cleared when the transfer is * entirely done. */ InstancePtr->IsBusy = TRUE; /* * Set up buffer pointers. */ InstancePtr->SendBufferPtr = SendBufPtr; InstancePtr->RecvBufferPtr = RecvBufPtr; InstancePtr->RequestedBytes = ByteCount; InstancePtr->RemainingBytes = ByteCount; /* * The first byte with every chip-select assertion is always * expected to be an instruction for flash interface mode */ Instruction = *InstancePtr->SendBufferPtr; for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) { if (Instruction == FlashInst[Index].OpCode) { break; } } /* * Set the RX FIFO threshold */ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT); /* * If the slave select is "Forced" or under manual control, * set the slave select now, before beginning the transfer. */ if (XQspiPs_IsManualChipSelect(InstancePtr)) { ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET); ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); } /* * Enable the device. */ XQspiPs_Enable(InstancePtr); if (Index < ARRAY_SIZE(FlashInst)) { CurrInst = &FlashInst[Index]; /* * Check for WRSR instruction which has different size for * Spansion (3 bytes) and Micron (2 bytes) */ if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) && (ByteCount == 3) ) { CurrInst->InstSize = 3; CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET; } } /* * If instruction not present in table */ if (Index == ARRAY_SIZE(FlashInst)) { /* * Assign current instruction, size and TXD register to be used. * The InstSize mentioned in case of instructions greater than 4 bytes * is not the actual size, but is indicative of the TXD register used. * The remaining bytes of the instruction will be transmitted * through TXD0 below. */ switch(ByteCount%4) { case XQSPIPS_SIZE_ONE: CurrInst->OpCode = Instruction; CurrInst->InstSize = XQSPIPS_SIZE_ONE; CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET; if(ByteCount > 4) { SwitchFlag = 1; } break; case XQSPIPS_SIZE_TWO: CurrInst->OpCode = Instruction; CurrInst->InstSize = XQSPIPS_SIZE_TWO; CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET; if(ByteCount > 4) { SwitchFlag = 1; } break; case XQSPIPS_SIZE_THREE: CurrInst->OpCode = Instruction; CurrInst->InstSize = XQSPIPS_SIZE_THREE; CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET; if(ByteCount > 4) { SwitchFlag = 1; } break; default: CurrInst->OpCode = Instruction; CurrInst->InstSize = XQSPIPS_SIZE_FOUR; CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET; break; } } /* * If the instruction size in not 4 bytes then the data received needs * to be shifted */ if( CurrInst->InstSize != 4 ) { InstancePtr->ShiftReadData = 1; } else { InstancePtr->ShiftReadData = 0; } TransCount = 0; /* Get the complete command (flash inst + address/data) */ Data = *((u32 *)InstancePtr->SendBufferPtr); InstancePtr->SendBufferPtr += CurrInst->InstSize; InstancePtr->RemainingBytes -= CurrInst->InstSize; if (InstancePtr->RemainingBytes < 0) { InstancePtr->RemainingBytes = 0; } /* Write the command to the FIFO */ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, CurrInst->TxOffset, Data); ++TransCount; /* * If switching from TXD1/2/3 to TXD0, then start transfer and * check for FIFO empty */ if(SwitchFlag == 1) { SwitchFlag = 0; /* * If, in Manual Start mode, start the transfer. */ if (XQspiPs_IsManualStart(InstancePtr)) { ConfigReg = XQspiPs_ReadReg( InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_MANSTRT_MASK; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); } /* * Wait for the transfer to finish by polling Tx fifo status. */ do { StatusReg = XQspiPs_ReadReg( InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET); } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0); } /* * Check if manual start is selected and store it in a * local varibale for reference. This is to avoid reading * the config register everytime. */ IsManualStart = XQspiPs_IsManualStart(InstancePtr); /* * Fill the DTR/FIFO with as many bytes as it will take (or as * many as we have to send). */ while ((InstancePtr->RemainingBytes > 0) && (TransCount < XQSPIPS_FIFO_DEPTH)) { XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_TXD_00_OFFSET, *((u32 *)InstancePtr->SendBufferPtr)); InstancePtr->SendBufferPtr += 4; InstancePtr->RemainingBytes -= 4; if (InstancePtr->RemainingBytes < 0) { InstancePtr->RemainingBytes = 0; } ++TransCount; } while((InstancePtr->RemainingBytes > 0) || (InstancePtr->RequestedBytes > 0)) { /* * Fill the TX FIFO with RX threshold no. of entries (or as * many as we have to send, in case that's less). */ while ((InstancePtr->RemainingBytes > 0) && (TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_TXD_00_OFFSET, *((u32 *)InstancePtr->SendBufferPtr)); InstancePtr->SendBufferPtr += 4; InstancePtr->RemainingBytes -= 4; if (InstancePtr->RemainingBytes < 0) { InstancePtr->RemainingBytes = 0; } ++TransCount; } /* * If, in Manual Start mode, start the transfer. */ if (IsManualStart == TRUE) { ConfigReg = XQspiPs_ReadReg( InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_MANSTRT_MASK; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); } /* * Reset TransCount - this is only used to fill TX FIFO * in the above loop; * RxCount is used to keep track of data received */ TransCount = 0; /* * Wait for RX FIFO to reach threshold (or) * TX FIFO to become empty. * The latter check is required for * small transfers (<32 words) and * when the last chunk in a large data transfer is < 32 words. */ do { StatusReg = XQspiPs_ReadReg( InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET); } while ( ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) && ((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0) ); /* * A transmit has just completed. Process received data * and check for more data to transmit. * First get the data received as a result of the * transmit that just completed. Receive data based on the * count obtained while filling tx fifo. Always get * the received data, but only fill the receive * buffer if it points to something (the upper layer * software may not care to receive data). */ while ((InstancePtr->RequestedBytes > 0) && (RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT )) { u32 Data; RxCount++; if (InstancePtr->RecvBufferPtr != NULL) { if (InstancePtr->RequestedBytes < 4) { Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPS_RXD_OFFSET); XQspiPs_GetReadData(InstancePtr, Data, InstancePtr->RequestedBytes); } else { (*(u32 *)InstancePtr->RecvBufferPtr) = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPS_RXD_OFFSET); InstancePtr->RecvBufferPtr += 4; InstancePtr->RequestedBytes -= 4; if (InstancePtr->RequestedBytes < 0) { InstancePtr->RequestedBytes = 0; } } } else { Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPS_RXD_OFFSET); InstancePtr->RequestedBytes -= 4; } } RxCount = 0; } /* * If the Slave select lines are being manually controlled, disable * them because the transfer is complete. */ if (XQspiPs_IsManualChipSelect(InstancePtr)) { ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_SSCTRL_MASK; XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); } /* * Clear the busy flag. */ InstancePtr->IsBusy = FALSE; /* * Disable the device. */ XQspiPs_Disable(InstancePtr); /* * Reset the RX FIFO threshold to one */ XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); return XST_SUCCESS; }
/** * * The interrupt handler for QSPI interrupts. This function must be connected * by the user to an interrupt controller. * * The interrupts that are handled are: * * * - Data Transmit Register (FIFO) Empty. This interrupt is generated when the * transmit register or FIFO is empty. The driver uses this interrupt during a * transmission to continually send/receive data until the transfer is done. * * - Data Transmit Register (FIFO) Underflow. This interrupt is generated when * the QSPI device, when configured as a slave, attempts to read an empty * DTR/FIFO. An empty DTR/FIFO usually means that software is not giving the * device data in a timely manner. No action is taken by the driver other than * to inform the upper layer software of the error. * * - Data Receive Register (FIFO) Overflow. This interrupt is generated when the * QSPI device attempts to write a received byte to an already full DRR/FIFO. * A full DRR/FIFO usually means software is not emptying the data in a timely * manner. No action is taken by the driver other than to inform the upper * layer software of the error. * * @param InstancePtr is a pointer to the XQspiPs instance. * * @return None. * * @note * * The slave select register is being set to deselect the slave when a transfer * is complete. * ******************************************************************************/ void XQspiPs_InterruptHandler(void *InstancePtr) { XQspiPs *QspiPtr = (XQspiPs *)InstancePtr; u32 IntrStatus; u32 ConfigReg; u32 Data; u32 TransCount; u32 Count = 0; unsigned BytesDone; /* Number of bytes done so far. */ Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(QspiPtr->IsReady == XIL_COMPONENT_IS_READY); /* * Immediately clear the interrupts in case the ISR causes another * interrupt to be generated. If we clear at the end of the ISR, * we may miss newly generated interrupts. This occurs because we * transmit from within the ISR, which could potentially cause another * TX_EMPTY interrupt. */ IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET); XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET, (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK)); XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET, XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK | XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK); if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) || (IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) { /* * Rx FIFO has just reached threshold no. of entries. * Read threshold no. of entries from RX FIFO * Another possiblity of entering this loop is when * the last byte has been transmitted and TX FIFO is empty, * in which case, read all the data from RX FIFO. * Always get the received data, but only fill the * receive buffer if it is not null (it can be null when * the device does not care to receive data). */ TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes; if (TransCount % 4) { TransCount = TransCount/4 + 1; } else { TransCount = TransCount/4; } while ((Count < TransCount) && (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { if (QspiPtr->RecvBufferPtr != NULL) { if (QspiPtr->RequestedBytes < 4) { Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress, XQSPIPS_RXD_OFFSET); XQspiPs_GetReadData(QspiPtr, Data, QspiPtr->RequestedBytes); } else { (*(u32 *)QspiPtr->RecvBufferPtr) = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress, XQSPIPS_RXD_OFFSET); QspiPtr->RecvBufferPtr += 4; QspiPtr->RequestedBytes -= 4; if (QspiPtr->RequestedBytes < 0) { QspiPtr->RequestedBytes = 0; } } } else { XQspiPs_ReadReg(QspiPtr->Config.BaseAddress, XQSPIPS_RXD_OFFSET); QspiPtr->RequestedBytes -= 4; if (QspiPtr->RequestedBytes < 0) { QspiPtr->RequestedBytes = 0; } } Count++; } Count = 0; /* * Interrupt asserted as TX_OW got asserted * See if there is more data to send. * Fill TX FIFO with RX threshold no. of entries or * remaining entries (in case that is less than threshold) */ while ((QspiPtr->RemainingBytes > 0) && (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) { /* * Send more data. */ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_TXD_00_OFFSET, *((u32 *)QspiPtr->SendBufferPtr)); QspiPtr->SendBufferPtr += 4; QspiPtr->RemainingBytes -= 4; if (QspiPtr->RemainingBytes < 0) { QspiPtr->RemainingBytes = 0; } Count++; } if ((QspiPtr->RemainingBytes == 0) && (QspiPtr->RequestedBytes == 0)) { /* * No more data to send. Disable the interrupt * and inform the upper layer software that the * transfer is done. The interrupt will be re-enabled * when another transfer is initiated. */ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK | XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK); /* * If the Slave select is being manually controlled, * disable it because the transfer is complete. */ if (XQspiPs_IsManualChipSelect(InstancePtr)) { ConfigReg = XQspiPs_ReadReg( QspiPtr->Config.BaseAddress, XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_SSCTRL_MASK; XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); } /* * Clear the busy flag. */ QspiPtr->IsBusy = FALSE; /* * Disable the device. */ XQspiPs_Disable(QspiPtr); /* * Reset the RX FIFO threshold to one */ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); QspiPtr->StatusHandler(QspiPtr->StatusRef, XST_SPI_TRANSFER_DONE, QspiPtr->RequestedBytes); } else { /* * Enable the TXOW interrupt. */ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK | XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK); /* * If, in Manual Start mode, start the transfer. */ if (XQspiPs_IsManualStart(QspiPtr)) { ConfigReg = XQspiPs_ReadReg( QspiPtr->Config.BaseAddress, XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_MANSTRT_MASK; XQspiPs_WriteReg( QspiPtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); } } } /* * Check for overflow and underflow errors. */ if (IntrStatus & XQSPIPS_IXR_RXOVR_MASK) { BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes; QspiPtr->IsBusy = FALSE; /* * If the Slave select lines is being manually controlled, * disable it because the transfer is complete. */ if (XQspiPs_IsManualChipSelect(InstancePtr)) { ConfigReg = XQspiPs_ReadReg( QspiPtr->Config.BaseAddress, XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_SSCTRL_MASK; XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); } /* * Disable the device. */ XQspiPs_Disable(QspiPtr); /* * Reset the RX FIFO threshold to one */ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); QspiPtr->StatusHandler(QspiPtr->StatusRef, XST_SPI_RECEIVE_OVERRUN, BytesDone); } if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) { BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes; QspiPtr->IsBusy = FALSE; /* * If the Slave select lines is being manually controlled, * disable it because the transfer is complete. */ if (XQspiPs_IsManualChipSelect(InstancePtr)) { ConfigReg = XQspiPs_ReadReg( QspiPtr->Config.BaseAddress, XQSPIPS_CR_OFFSET); ConfigReg |= XQSPIPS_CR_SSCTRL_MASK; XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg); } /* * Disable the device. */ XQspiPs_Disable(QspiPtr); /* * Reset the RX FIFO threshold to one */ XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE); QspiPtr->StatusHandler(QspiPtr->StatusRef, XST_SPI_TRANSMIT_UNDERRUN, BytesDone); } }