XtensaCPU *cpu_xtensa_init(const char *cpu_model) { XtensaCPU *cpu; CPUXtensaState *env; const XtensaConfig *config = NULL; XtensaConfigList *core = xtensa_cores; for (; core; core = core->next) if (strcmp(core->config->name, cpu_model) == 0) { config = core->config; break; } if (config == NULL) { return NULL; } cpu = XTENSA_CPU(object_new(TYPE_XTENSA_CPU)); env = &cpu->env; env->config = config; xtensa_irq_init(env); object_property_set_bool(OBJECT(cpu), true, "realized", NULL); return cpu; }
/* CPUClass::reset() */ static void xtensa_cpu_reset(CPUState *s) { XtensaCPU *cpu = XTENSA_CPU(s); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); CPUXtensaState *env = &cpu->env; xcc->parent_reset(s); env->exception_taken = 0; env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; env->sregs[LITBASE] &= ~1; #ifndef CONFIG_USER_ONLY env->sregs[PS] = xtensa_option_enabled(env->config, XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; env->pending_irq_level = 0; #else env->sregs[PS] = (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) ? PS_WOE : 0) | PS_UM | (3 << PS_RING_SHIFT); #endif env->sregs[VECBASE] = env->config->vecbase; env->sregs[IBREAKENABLE] = 0; env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; env->sregs[CACHEATTR] = 0x22222222; env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; env->sregs[CONFIGID0] = env->config->configid[0]; env->sregs[CONFIGID1] = env->config->configid[1]; #ifndef CONFIG_USER_ONLY reset_mmu(env); s->halted = env->runstall; #endif }
static void xtensa_cpu_initfn(Object *obj) { XtensaCPU *cpu = XTENSA_CPU(obj); CPUXtensaState *env = &cpu->env; cpu_exec_init(env); }
static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) { XtensaCPU *cpu = XTENSA_CPU(cs); info->private_data = cpu->env.config->isa; info->print_insn = print_insn_xtensa; }
static bool xtensa_cpu_has_work(CPUState *cs) { #ifndef CONFIG_USER_ONLY XtensaCPU *cpu = XTENSA_CPU(cs); return !cpu->env.runstall && cpu->env.pending_irq_level; #else return true; #endif }
int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; uint32_t tmp; const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; if (n < 0 || n >= env->config->gdb_regmap.num_regs) { return 0; } tmp = ldl_p(mem_buf); switch (reg->type) { case 9: /*pc*/ env->pc = tmp; break; case 1: /*ar*/ env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp; xtensa_sync_window_from_phys(env); break; case 2: /*SR*/ env->sregs[reg->targno & 0xff] = tmp; break; case 3: /*UR*/ env->uregs[reg->targno & 0xff] = tmp; break; case 4: /*f*/ switch (reg->size) { case 4: env->fregs[reg->targno & 0x0f].f32[FP_F32_LOW] = make_float32(tmp); return 4; case 8: env->fregs[reg->targno & 0x0f].f64 = make_float64(tmp); return 8; default: return 0; } case 8: /*a*/ env->regs[reg->targno & 0x0f] = tmp; break; default: qemu_log_mask(LOG_UNIMP, "%s to reg %d of unsupported type %d\n", __func__, n, reg->type); return 0; } return 4; }
void xtensa_cpu_do_interrupt(CPUState *cs) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; if (env->exception_index == EXC_IRQ) { qemu_log_mask(CPU_LOG_INT, "%s(EXC_IRQ) level = %d, cintlevel = %d, " "pc = %08x, a0 = %08x, ps = %08x, " "intset = %08x, intenable = %08x, " "ccount = %08x\n", __func__, env->pending_irq_level, xtensa_get_cintlevel(env), env->pc, env->regs[0], env->sregs[PS], env->sregs[INTSET], env->sregs[INTENABLE], env->sregs[CCOUNT]); handle_interrupt(env); } switch (env->exception_index) { case EXC_WINDOW_OVERFLOW4: case EXC_WINDOW_UNDERFLOW4: case EXC_WINDOW_OVERFLOW8: case EXC_WINDOW_UNDERFLOW8: case EXC_WINDOW_OVERFLOW12: case EXC_WINDOW_UNDERFLOW12: case EXC_KERNEL: case EXC_USER: case EXC_DOUBLE: case EXC_DEBUG: qemu_log_mask(CPU_LOG_INT, "%s(%d) " "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n", __func__, env->exception_index, env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]); if (env->config->exception_vector[env->exception_index]) { env->pc = relocated_vector(env, env->config->exception_vector[env->exception_index]); env->exception_taken = 1; } else { qemu_log("%s(pc = %08x) bad exception_index: %d\n", __func__, env->pc, env->exception_index); } break; case EXC_IRQ: break; default: qemu_log("%s(pc = %08x) unknown exception_index: %d\n", __func__, env->pc, env->exception_index); break; } check_interrupts(env); }
static void xtensa_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); XtensaCPU *cpu = XTENSA_CPU(obj); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); CPUXtensaState *env = &cpu->env; static bool tcg_inited; cs->env_ptr = env; env->config = xcc->config; if (tcg_enabled() && !tcg_inited) { tcg_inited = true; xtensa_translate_init(); } }
static void xtensa_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); XtensaCPU *cpu = XTENSA_CPU(obj); CPUXtensaState *env = &cpu->env; static bool tcg_inited; cs->env_ptr = env; cpu_exec_init(env); if (tcg_enabled() && !tcg_inited) { tcg_inited = true; xtensa_translate_init(); cpu_set_debug_excp_handler(xtensa_breakpoint_handler); } }
int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; unsigned i; if (n < 0 || n >= env->config->gdb_regmap.num_regs) { return 0; } switch (reg->type) { case 9: /*pc*/ return gdb_get_reg32(mem_buf, env->pc); case 1: /*ar*/ xtensa_sync_phys_from_window(env); return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff) % env->config->nareg]); case 2: /*SR*/ return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]); case 3: /*UR*/ return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]); case 4: /*f*/ i = reg->targno & 0x0f; switch (reg->size) { case 4: return gdb_get_reg32(mem_buf, float32_val(env->fregs[i].f32[FP_F32_LOW])); case 8: return gdb_get_reg64(mem_buf, float64_val(env->fregs[i].f64)); default: return 0; } case 8: /*a*/ return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]); default: qemu_log_mask(LOG_UNIMP, "%s from reg %d of unsupported type %d\n", __func__, n, reg->type); return 0; } }
static void xtensa_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); XtensaCPU *cpu = XTENSA_CPU(obj); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); CPUXtensaState *env = &cpu->env; cs->env_ptr = env; env->config = xcc->config; #ifndef CONFIG_USER_ONLY env->address_space_er = g_malloc(sizeof(*env->address_space_er)); env->system_er = g_malloc(sizeof(*env->system_er)); memory_region_init_io(env->system_er, NULL, NULL, env, "er", UINT64_C(0x100000000)); address_space_init(env->address_space_er, env->system_er, "ER"); #endif }
/* CPUClass::reset() */ static void xtensa_cpu_reset(CPUState *s) { XtensaCPU *cpu = XTENSA_CPU(s); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); CPUXtensaState *env = &cpu->env; xcc->parent_reset(s); env->exception_taken = 0; env->pc = env->config->exception_vector[EXC_RESET]; env->sregs[LITBASE] &= ~1; env->sregs[PS] = xtensa_option_enabled(env->config, XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; env->sregs[VECBASE] = env->config->vecbase; env->sregs[IBREAKENABLE] = 0; env->pending_irq_level = 0; reset_mmu(env); }
static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); Error *local_err = NULL; #ifndef CONFIG_USER_ONLY xtensa_irq_init(&XTENSA_CPU(dev)->env); #endif cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; } cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; qemu_init_vcpu(cs); xcc->parent_realize(dev, errp); }
CPUXtensaState *cpu_xtensa_init(const char *cpu_model) { static int tcg_inited; static int debug_handler_inited; XtensaCPU *cpu; CPUXtensaState *env; const XtensaConfig *config = NULL; XtensaConfigList *core = xtensa_cores; for (; core; core = core->next) if (strcmp(core->config->name, cpu_model) == 0) { config = core->config; break; } if (config == NULL) { return NULL; } cpu = XTENSA_CPU(object_new(TYPE_XTENSA_CPU)); env = &cpu->env; env->config = config; if (!tcg_inited) { tcg_inited = 1; xtensa_translate_init(); } if (!debug_handler_inited && tcg_enabled()) { debug_handler_inited = 1; prev_debug_excp_handler = cpu_set_debug_excp_handler(breakpoint_handler); } xtensa_irq_init(env); qemu_init_vcpu(env); return env; }
void tlb_fill(CPUState *cs, target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; uint32_t paddr; uint32_t page_size; unsigned access; int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx, &paddr, &page_size, &access); qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__, vaddr, is_write, mmu_idx, paddr, ret); if (ret == 0) { tlb_set_page(cs, vaddr & TARGET_PAGE_MASK, paddr & TARGET_PAGE_MASK, access, mmu_idx, page_size); } else { cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); } }
static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) { XtensaCPU *cpu = XTENSA_CPU(cs); cpu->env.pc = value; }
static bool xtensa_cpu_has_work(CPUState *cs) { XtensaCPU *cpu = XTENSA_CPU(cs); return cpu->env.pending_irq_level; }
static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) { #ifdef TARGET_WORDS_BIGENDIAN int be = 1; #else int be = 0; #endif MemoryRegion *system_memory = get_system_memory(); XtensaCPU *cpu = NULL; CPUXtensaState *env = NULL; MemoryRegion *system_io; DriveInfo *dinfo; pflash_t *flash = NULL; QemuOpts *machine_opts = qemu_get_machine_opts(); const char *kernel_filename = qemu_opt_get(machine_opts, "kernel"); const char *kernel_cmdline = qemu_opt_get(machine_opts, "append"); const char *dtb_filename = qemu_opt_get(machine_opts, "dtb"); const char *initrd_filename = qemu_opt_get(machine_opts, "initrd"); const unsigned system_io_size = 224 * 1024 * 1024; int n; for (n = 0; n < smp_cpus; n++) { cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); env = &cpu->env; env->sregs[PRID] = n; qemu_register_reset(xtfpga_reset, cpu); /* Need MMU initialized prior to ELF loading, * so that ELF gets loaded into virtual addresses */ cpu_reset(CPU(cpu)); } if (env) { XtensaMemory sysram = env->config->sysram; sysram.location[0].size = machine->ram_size; xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", system_memory); xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", system_memory); xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", system_memory); xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", system_memory); xtensa_create_memory_regions(&sysram, "xtensa.sysram", system_memory); } system_io = g_malloc(sizeof(*system_io)); memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", system_io_size); memory_region_add_subregion(system_memory, board->io[0], system_io); if (board->io[1]) { MemoryRegion *io = g_malloc(sizeof(*io)); memory_region_init_alias(io, NULL, "xtfpga.io.cached", system_io, 0, system_io_size); memory_region_add_subregion(system_memory, board->io[1], io); } xtfpga_fpga_init(system_io, 0x0d020000); if (nd_table[0].used) { xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, xtensa_get_extint(env, 1), nd_table); } if (!serial_hds[0]) { serial_hds[0] = qemu_chr_new("serial0", "null"); } serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0), 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); dinfo = drive_get(IF_PFLASH, 0, 0); if (dinfo) { flash = xtfpga_flash_init(system_io, board, dinfo, be); } /* Use presence of kernel file name as 'boot from SRAM' switch. */ if (kernel_filename) { uint32_t entry_point = env->pc; size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ uint32_t tagptr = env->config->sysrom.location[0].addr + board->sram_size; uint32_t cur_tagptr; BpMemInfo memory_location = { .type = tswap32(MEMORY_TYPE_CONVENTIONAL), .start = tswap32(env->config->sysram.location[0].addr), .end = tswap32(env->config->sysram.location[0].addr + machine->ram_size), }; uint32_t lowmem_end = machine->ram_size < 0x08000000 ? machine->ram_size : 0x08000000; uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); lowmem_end += env->config->sysram.location[0].addr; cur_lowmem += env->config->sysram.location[0].addr; xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", system_memory); if (kernel_cmdline) { bp_size += get_tag_size(strlen(kernel_cmdline) + 1); } if (dtb_filename) { bp_size += get_tag_size(sizeof(uint32_t)); } if (initrd_filename) { bp_size += get_tag_size(sizeof(BpMemInfo)); } /* Put kernel bootparameters to the end of that SRAM */ tagptr = (tagptr - bp_size) & ~0xff; cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, sizeof(memory_location), &memory_location); if (kernel_cmdline) { cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, strlen(kernel_cmdline) + 1, kernel_cmdline); } #ifdef CONFIG_FDT if (dtb_filename) { int fdt_size; void *fdt = load_device_tree(dtb_filename, &fdt_size); uint32_t dtb_addr = tswap32(cur_lowmem); if (!fdt) { error_report("could not load DTB '%s'", dtb_filename); exit(EXIT_FAILURE); } cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, sizeof(dtb_addr), &dtb_addr); cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096); } #else if (dtb_filename) { error_report("could not load DTB '%s': " "FDT support is not configured in QEMU", dtb_filename); exit(EXIT_FAILURE); } #endif if (initrd_filename) { BpMemInfo initrd_location = { 0 }; int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, lowmem_end - cur_lowmem); if (initrd_size < 0) { initrd_size = load_image_targphys(initrd_filename, cur_lowmem, lowmem_end - cur_lowmem); } if (initrd_size < 0) { error_report("could not load initrd '%s'", initrd_filename); exit(EXIT_FAILURE); } initrd_location.start = tswap32(cur_lowmem); initrd_location.end = tswap32(cur_lowmem + initrd_size); cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, sizeof(initrd_location), &initrd_location); cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096); } cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); env->regs[2] = tagptr; uint64_t elf_entry; uint64_t elf_lowaddr; int success = load_elf(kernel_filename, translate_phys_addr, cpu, &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0); if (success > 0) { entry_point = elf_entry; } else { hwaddr ep; int is_linux; success = load_uimage(kernel_filename, &ep, NULL, &is_linux, translate_phys_addr, cpu); if (success > 0 && is_linux) { entry_point = ep; } else { error_report("could not load kernel '%s'", kernel_filename); exit(EXIT_FAILURE); } } if (entry_point != env->pc) { uint8_t boot[] = { #ifdef TARGET_WORDS_BIGENDIAN 0x60, 0x00, 0x08, /* j 1f */ 0x00, /* .literal_position */ 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ /* 1: */ 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 0x0a, 0x00, 0x00, /* jx a0 */ #else 0x06, 0x02, 0x00, /* j 1f */ 0x00, /* .literal_position */ 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ /* 1: */ 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 0xa0, 0x00, 0x00, /* jx a0 */ #endif }; uint32_t entry_pc = tswap32(entry_point); uint32_t entry_a2 = tswap32(tagptr); memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); cpu_physical_memory_write(env->pc, boot, sizeof(boot)); } } else { if (flash) { MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); uint32_t size = env->config->sysrom.location[0].size; if (board->flash->size - board->flash->boot_base < size) { size = board->flash->size - board->flash->boot_base; } memory_region_init_alias(flash_io, NULL, "xtfpga.flash", flash_mr, board->flash->boot_base, size); memory_region_add_subregion(system_memory, env->config->sysrom.location[0].addr, flash_io); } else { xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", system_memory); } } }