u32 XHdcp22_mmult_Get_A_TotalBytes(XHdcp22_mmult *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return (XHDCP22_MMULT_CTRL_ADDR_A_HIGH - XHDCP22_MMULT_CTRL_ADDR_A_BASE + 1);
}
u32 XHdcp22_mmult_Get_A_Depth(XHdcp22_mmult *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return XHDCP22_MMULT_CTRL_DEPTH_A;
}
u32 XHdcp22_mmult_Get_U_BitWidth(XHdcp22_mmult *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return XHDCP22_MMULT_CTRL_WIDTH_U;
}
u32 XHdcp22_mmult_Get_A_HighAddress(XHdcp22_mmult *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return (InstancePtr->Config.BaseAddress + XHDCP22_MMULT_CTRL_ADDR_A_HIGH);
}
/**
*
* Run a self-test on the driver/device. This is a destructive test.
*
* This involves forcing interrupts into the controller and verifying that they
* are recognized and can be acknowledged. This test will not succeed if the
* interrupt controller has been started in real mode such that interrupts
* cannot be forced.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
*
* @return
* - XST_SUCCESS if self-test is successful.
* - XST_INTC_FAIL_SELFTEST if the Interrupt controller fails the
* self-test. It will fail the self test if the device has
* previously been started in real mode.
*
* @note None.
*
******************************************************************************/
int XIntc_SelfTest(XIntc * InstancePtr)
{
u32 CurrentISR;
u32 Temp;
/*
* Assert the arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Acknowledge all pending interrupts by reading the interrupt status
* register and writing the value to the acknowledge register
*/
Temp = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, Temp);
/*
* Verify that there are no interrupts by reading the interrupt status
*/
CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
/*
* ISR should be zero after all interrupts are acknowledged
*/
if (CurrentISR != 0) {
return XST_INTC_FAIL_SELFTEST;
}
/*
* Set a bit in the ISR which simulates an interrupt
*/
XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, XIN_TEST_MASK);
/*
* Verify that it was set
*/
CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
if (CurrentISR != XIN_TEST_MASK) {
return XST_INTC_FAIL_SELFTEST;
}
/*
* Acknowledge the interrupt
*/
XIntc_Out32(InstancePtr->BaseAddress + XIN_IAR_OFFSET, XIN_TEST_MASK);
/*
* Read back the ISR to verify that the interrupt is gone
*/
CurrentISR = XIntc_In32(InstancePtr->BaseAddress + XIN_ISR_OFFSET);
if (CurrentISR != 0) {
return XST_INTC_FAIL_SELFTEST;
}
return XST_SUCCESS;
}
/**
*
* Allows software to simulate an interrupt in the interrupt controller. This
* function will only be successful when the interrupt controller has been
* started in simulation mode. Once it has been started in real mode,
* interrupts cannot be simulated. A simulated interrupt allows the interrupt
* controller to be tested without any device to drive an interrupt input
* signal into it. In Cascade mode writes to ISR of appropraite Slave
* controller depending on Id.
*
* @param InstancePtr is a pointer to the XIntc instance to be worked on.
* @param Id is the interrupt ID for which to simulate an interrupt.
*
* @return
* - XST_SUCCESS if successful
* - XST_FAILURE if the interrupt could not be
* simulated because the interrupt controller is or
* has previously been in real mode.
*
* @note None.
*
******************************************************************************/
int XIntc_SimulateIntr(XIntc * InstancePtr, u8 Id)
{
u32 Mask;
u32 MasterEnable;
XIntc_Config *CfgPtr;
int Index;
int DeviceId;
/*
* Assert the arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Id < XPAR_INTC_MAX_NUM_INTR_INPUTS);
/* Get the contents of the master enable register and determine if
* hardware interrupts have already been enabled, if so, this is a write
* once bit such that simulation can't be done at this point because
* the ISR register is no longer writable by software
*/
MasterEnable = XIntc_In32(InstancePtr->BaseAddress + XIN_MER_OFFSET);
if (MasterEnable & XIN_INT_HARDWARE_ENABLE_MASK) {
return XST_FAILURE;
}
if (Id > 31) {
DeviceId = Id/32;
CfgPtr = XIntc_LookupConfig(Id/32);
Mask = XIntc_BitPosMask[Id%32];
XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET, Mask);
/* Generate interrupt for 31 by writing to Interrupt Status
* register of parent controllers. Primary controller ISR
* will be written last in the loop
*/
Mask = XIntc_BitPosMask[31];
for (Index = DeviceId - 1; Index >= 0; Index--)
{
CfgPtr = XIntc_LookupConfig(Index);
XIntc_Out32(CfgPtr->BaseAddress + XIN_ISR_OFFSET,
Mask);
}
}
else {
/*
* The Id is used to create the appropriate mask for the
* desired bit position.
*/
Mask = XIntc_BitPosMask[Id];
/*
* Enable the selected interrupt source by reading the interrupt
* enable register and then modifying only the specified
* interrupt id enable
*/
XIntc_Out32(InstancePtr->BaseAddress + XIN_ISR_OFFSET, Mask);
}
/* indicate the interrupt was successfully simulated */
return XST_SUCCESS;
}
/**
*
* This function runs a self-test on the driver and hardware device. This self
* test performs a local loopback and verifies data can be sent and received.
*
* The time for this test is proportional to the baud rate that has been set
* prior to calling this function.
*
* The mode and control registers are restored before return.
*
* @param InstancePtr is a pointer to the XUartPs instance
*
* @return
* - XST_SUCCESS if the test was successful
* - XST_UART_TEST_FAIL if the test failed looping back the data
*
* @note
*
* This function can hang if the hardware is not functioning properly.
*
******************************************************************************/
int XUartPs_SelfTest(XUartPs *InstancePtr)
{
int Status = XST_SUCCESS;
u32 IntrRegister;
u32 ModeRegister;
u8 Index;
/*
* Assert validates the input arguments
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/*
* Disable all interrupts in the interrupt disable register
*/
IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
XUARTPS_IMR_OFFSET);
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
XUARTPS_IXR_MASK);
/*
* Setup for local loopback
*/
ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
XUARTPS_MR_OFFSET);
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
((ModeRegister & (~XUARTPS_MR_CHMODE_MASK)) |
XUARTPS_MR_CHMODE_L_LOOP));
/*
* Send a number of bytes and receive them, one at a time.
*/
for (Index = 0; Index < XUARTPS_TOTAL_BYTES; Index++) {
/*
* Send out the byte and if it was not sent then the failure
* will be caught in the comparison at the end
*/
XUartPs_Send(InstancePtr, &TestString[Index], 1);
/*
* Wait until the byte is received. This can hang if the HW
* is broken. Watch for the FIFO empty flag to be false.
*/
while (!(XUartPs_IsReceiveData(InstancePtr->Config.
BaseAddress)));
/*
* Receive the byte
*/
XUartPs_Recv(InstancePtr, &ReturnString[Index], 1);
}
/*
* Compare the bytes received to the bytes sent to verify the exact data
* was received
*/
for (Index = 0; Index < XUARTPS_TOTAL_BYTES; Index++) {
if (TestString[Index] != ReturnString[Index]) {
Status = XST_UART_TEST_FAIL;
}
}
/*
* Restore the registers which were altered to put into polling and
* loopback modes so that this test is not destructive
*/
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
IntrRegister);
XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
ModeRegister);
return Status;
}
/**
* This function receives a buffer in polled mode as a slave.
*
* @param InstancePtr is a pointer to the XIicPs instance.
* @param MsgPtr is the pointer to the receive buffer.
* @param ByteCount is the number of bytes to be received.
*
* @return
* - XST_SUCCESS if everything went well.
* - XST_FAILURE if timed out.
*
* @note This receive routine is for polled mode transfer only.
*
****************************************************************************/
s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
{
u32 IntrStatusReg;
u32 StatusReg;
u32 BaseAddr;
s32 Count;
/*
* Assert validates the input arguments.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(MsgPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
BaseAddr = InstancePtr->Config.BaseAddress;
InstancePtr->RecvBufferPtr = MsgPtr;
InstancePtr->RecvByteCount = ByteCount;
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
/*
* Clear the interrupt status register.
*/
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
/*
* Clear the status register.
*/
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
XIicPs_WriteReg(BaseAddr, XIICPS_SR_OFFSET, StatusReg);
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
Count = InstancePtr->RecvByteCount;
while (Count > (s32)0) {
/* Wait for master to put data */
while ((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) {
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
/*
* If master terminates the transfer before we get all
* the data or the master tries to read from us,
* it is an error.
*/
IntrStatusReg = XIicPs_ReadReg(BaseAddr,
XIICPS_ISR_OFFSET);
if (((IntrStatusReg & (XIICPS_IXR_DATA_MASK |
XIICPS_IXR_COMP_MASK))!=0x0U) &&
((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) &&
((InstancePtr->RecvByteCount > 0) != 0x0U)) {
return (s32)XST_FAILURE;
}
/*
* Clear the interrupt status register.
*/
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
IntrStatusReg);
}
/*
* Read all data from FIFO.
*/
while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
((InstancePtr->RecvByteCount > 0) != 0x0U)){
XIicPs_RecvByte(InstancePtr);
StatusReg = XIicPs_ReadReg(BaseAddr,
XIICPS_SR_OFFSET);
}
Count = InstancePtr->RecvByteCount;
}
return (s32)XST_SUCCESS;
}
/**
* This function sends a buffer in polled mode as a slave.
*
* @param InstancePtr is a pointer to the XIicPs instance.
* @param MsgPtr is the pointer to the send buffer.
* @param ByteCount is the number of bytes to be sent.
*
* @return
* - XST_SUCCESS if everything went well.
* - XST_FAILURE if master sends us data or master terminates the
* transfer before all data has sent out.
*
* @note This send routine is for polled mode transfer only.
*
****************************************************************************/
s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
{
u32 IntrStatusReg;
u32 StatusReg;
u32 BaseAddr;
s32 Tmp;
s32 BytesToSend;
s32 Error = 0;
s32 Status = (s32)XST_SUCCESS;
u32 Value;
/*
* Assert validates the input arguments.
*/
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(MsgPtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
BaseAddr = InstancePtr->Config.BaseAddress;
InstancePtr->SendBufferPtr = MsgPtr;
InstancePtr->SendByteCount = ByteCount;
/*
* Use RXRW bit in status register to wait master to start a read.
*/
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
while (((StatusReg & XIICPS_SR_RXRW_MASK) == 0U) &&
((!Error) != 0)) {
/*
* If master tries to send us data, it is an error.
*/
if ((StatusReg & XIICPS_SR_RXDV_MASK) != 0x0U) {
Error = 1;
}
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
}
if (Error != 0) {
Status = (s32)XST_FAILURE;
} else {
/*
* Clear the interrupt status register.
*/
IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
/*
* Send data as long as there is more data to send and
* there are no errors.
*/
Value = (InstancePtr->SendByteCount > (s32)0) &&
((!Error) != 0);
while (Value != (u32)0x00U) {
/*
* Find out how many can be sent.
*/
BytesToSend = InstancePtr->SendByteCount;
if (BytesToSend > (s32)(XIICPS_FIFO_DEPTH)) {
BytesToSend = (s32)(XIICPS_FIFO_DEPTH);
}
for(Tmp = 0; Tmp < BytesToSend; Tmp ++) {
XIicPs_SendByte(InstancePtr);
}
StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
/*
* Wait for master to read the data out of fifo.
*/
while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) &&
((!Error) != 0)) {
/*
* If master terminates the transfer before all data is
* sent, it is an error.
*/
IntrStatusReg = XIicPs_ReadReg(BaseAddr,
XIICPS_ISR_OFFSET);
if ((IntrStatusReg & XIICPS_IXR_NACK_MASK) != 0x0U) {
Error = 1;
}
/* Clear ISR.
*/
XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
IntrStatusReg);
StatusReg = XIicPs_ReadReg(BaseAddr,
XIICPS_SR_OFFSET);
}
Value = (InstancePtr->SendByteCount > (s32)0U) &&
((!Error) != 0);
}
}
if (Error != 0) {
Status = (s32)XST_FAILURE;
}
return Status;
}