/**
*
* This function Registers the Exception Handlers
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
void XFsbl_RegisterHandlers(void)
{
Xil_ExceptionInit();
/*
* Initialize the vector table. Register the stub Handler for each
* exception.
*/
#ifdef ARMA53_64
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_SYNC_INT,
(Xil_ExceptionHandler)XFsbl_UndefHandler,(void *) 0);
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XFsbl_IrqHandler,(void *) 0);
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_FIQ_INT,
(Xil_ExceptionHandler)XFsbl_FiqHandler,(void *) 0);
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_SERROR_ABORT_INT,
(Xil_ExceptionHandler)XFsbl_DataAbortHandler,(void *) 0);
#else
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT,
(Xil_ExceptionHandler)XFsbl_UndefHandler,(void *) 0);
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_SWI_INT,
(Xil_ExceptionHandler)XFsbl_SvcHandler,(void *) 0);
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT,
(Xil_ExceptionHandler)XFsbl_PreFetchAbortHandler,(void *) 0);
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT,
(Xil_ExceptionHandler)XFsbl_DataAbortHandler,(void *) 0);
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XFsbl_IrqHandler,(void *) 0);
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_FIQ_INT,
(Xil_ExceptionHandler)XFsbl_FiqHandler,(void *) 0);
#endif
}
/**
*
* This function setups the interrupt system for an Spi device.
* This function is application specific since the actual system may or may not
* have an interrupt controller. The Spi device could be directly connected to
* a processor without an interrupt controller. The user should modify this
* function to fit the application.
*
* @param IntcInstancePtr is a pointer to the instance of the Intc device.
* @param SpiInstancePtr is a pointer to the instance of the Spi device.
* @param SpiIntrId is the interrupt Id for an SPI device.
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None.
*
******************************************************************************/
static int SpiSetupIntrSystem(XScuGic *IntcInstancePtr,
XSpiPs *SpiInstancePtr, u16 SpiIntrId)
{
int Status;
#ifndef TESTAPP_GEN
XScuGic_Config *IntcConfig; /* Instance of the interrupt controller */
Xil_ExceptionInit();
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
IntcInstancePtr);
#endif
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, SpiIntrId,
(Xil_ExceptionHandler)XSpiPs_InterruptHandler,
(void *)SpiInstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the Spi device.
*/
XScuGic_Enable(IntcInstancePtr, SpiIntrId);
#ifndef TESTAPP_GEN
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnable();
#endif
return XST_SUCCESS;
}
XStatus InitInterruptController(INTC* intc) {
int Status;
// Start the interrupt controller
#ifdef XPAR_INTC_0_DEVICE_ID
// Initialize the driver instance
RETURN_ON_FAILURE(XIntc_Initialize(intc, INTC_DEVICE_ID));
RETURN_ON_FAILURE(XIntc_Start(intc, XIN_REAL_MODE));
#else
XScuGic_Config *GicConfig;
GicConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
XScuGic_CfgInitialize(intc, GicConfig, GicConfig->CpuBaseAddress);
Status = XScuGic_SelfTest(intc);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#endif
Xil_ExceptionInit();
/*
* register the interrupt controller handler with the exception table.
* This is in fact the ISR dispatch routine, calling our ISRs
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler) INTC_HANDLER, intc);
Xil_ExceptionEnable();
return XST_SUCCESS;
}
/*
*
* This function setups the interrupt system so interrupts can occur for the
* DMA. This function assumes INTC component exists in the hardware system.
*
* @param AxiDmaPtr is a pointer to the instance of the DMA engine
* @param ReadIntrId is the read channel Interrupt ID.
* @param WriteIntrId is the write channel Interrupt ID.
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None.
*
******************************************************************************/
static int SetupIntrSystem(XAxiVdma *AxiVdmaPtr, u16 ReadIntrId,
u16 WriteIntrId)
{
int Status;
XIntc *IntcInstancePtr =&Intc;
/* Initialize the interrupt controller and connect the ISRs */
Status = XIntc_Initialize(IntcInstancePtr, XPAR_INTC_0_DEVICE_ID);
if (Status != XST_SUCCESS) {
xil_printf( "Failed init intc\r\n");
return XST_FAILURE;
}
Status = XIntc_Connect(IntcInstancePtr, ReadIntrId,
(XInterruptHandler)XAxiVdma_ReadIntrHandler, AxiVdmaPtr);
if (Status != XST_SUCCESS) {
xil_printf("Failed read channel connect intc %d\r\n", Status);
return XST_FAILURE;
}
Status = XIntc_Connect(IntcInstancePtr, WriteIntrId,
(XInterruptHandler)XAxiVdma_WriteIntrHandler, AxiVdmaPtr);
if (Status != XST_SUCCESS) {
xil_printf("Failed write channel connect intc %d\r\n", Status);
return XST_FAILURE;
}
/* Start the interrupt controller */
Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
xil_printf( "Failed to start intc\r\n");
return XST_FAILURE;
}
/* Enable interrupts from the hardware */
XIntc_Enable(IntcInstancePtr, ReadIntrId);
XIntc_Enable(IntcInstancePtr, WriteIntrId);
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_InterruptHandler,
(void *)IntcInstancePtr);
Xil_ExceptionEnable();
/* Register call-back functions
*/
XAxiVdma_SetCallBack(AxiVdmaPtr, XAXIVDMA_HANDLER_GENERAL, ReadCallBack,
(void *)AxiVdmaPtr, XAXIVDMA_READ);
XAxiVdma_SetCallBack(AxiVdmaPtr, XAXIVDMA_HANDLER_ERROR,
ReadErrorCallBack, (void *)AxiVdmaPtr, XAXIVDMA_READ);
XAxiVdma_SetCallBack(AxiVdmaPtr, XAXIVDMA_HANDLER_GENERAL,
WriteCallBack, (void *)AxiVdmaPtr, XAXIVDMA_WRITE);
XAxiVdma_SetCallBack(AxiVdmaPtr, XAXIVDMA_HANDLER_ERROR,
WriteErrorCallBack, (void *)AxiVdmaPtr, XAXIVDMA_WRITE);
return XST_SUCCESS;
}
void platform_setup_interrupts()
{
XIntc *intcp;
intcp = &intc;
XIntc_Initialize(intcp, XPAR_XPS_INTC_0_DEVICE_ID);
XIntc_Start(intcp, XIN_REAL_MODE);
/* Start the interrupt controller */
XIntc_MasterEnable(XPAR_XPS_INTC_0_BASEADDR);
#ifdef __PPC__
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(XExceptionHandler)XIntc_DeviceInterruptHandler,
(void*) XPAR_XPS_INTC_0_DEVICE_ID);
#elif __MICROBLAZE__
microblaze_register_handler((XInterruptHandler)XIntc_InterruptHandler, intcp);
#endif
platform_setup_timer();
#ifdef XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK
/* Enable timer and EMAC interrupts in the interrupt controller */
XIntc_EnableIntr(XPAR_XPS_INTC_0_BASEADDR,
#ifdef __MICROBLAZE__
PLATFORM_TIMER_INTERRUPT_MASK |
#endif
XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK);
#endif
}
int zynqMP_r5_gic_initialize() {
u32 Status;
Xil_ExceptionDisable();
XScuGic_Config *IntcConfig; /* The configuration parameters of the interrupt controller */
/*
* Initialize the interrupt controller driver
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(&InterruptController, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Register the interrupt handler to the hardware interrupt handling
* logic in the ARM processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler) zynqMP_r5_irq_isr,
&InterruptController);
Xil_ExceptionEnable();
return 0;
}
static int SetupIntrSystem(XScuGic * IntcInstancePtr, XAxiDma * AxiDmaPtr, u16 TxIntrId)
{
int Status;
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcInstancePtr, TxIntrId, 0xA0, 0x3);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(IntcInstancePtr, TxIntrId,(Xil_InterruptHandler)TxIntrHandler,AxiDmaPtr);
if (Status != XST_SUCCESS) {
return Status;
}
XScuGic_Enable(IntcInstancePtr, TxIntrId);
/* Enable interrupts from the hardware */
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler)XScuGic_InterruptHandler,(void *)IntcInstancePtr);
Xil_ExceptionEnable();
return XST_SUCCESS;
}
void platform_setup_interrupts()
{
XIntc *intcp;
intcp = &intc;
XIntc_Initialize(intcp, XPAR_INTC_0_DEVICE_ID);
XIntc_Start(intcp, XIN_REAL_MODE);
platform_setup_timer();
/*
* Initialize the exception table.
*/
Xil_ExceptionInit();
/*
* Register the interrupt controller handler with the exception table.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) XIntc_InterruptHandler,
intcp);
#ifdef XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK
/* Enable timer and EMAC interrupts in the interrupt controller */
XIntc_EnableIntr(XPAR_XPS_INTC_0_BASEADDR,
#ifdef __MICROBLAZE__
PLATFORM_TIMER_INTERRUPT_MASK |
#endif
XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK);
#endif
#ifdef XPAR_INTC_0_LLTEMAC_0_VEC_ID
#ifdef __MICROBLAZE__
XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
#endif
XIntc_Enable(intcp, XPAR_INTC_0_LLTEMAC_0_VEC_ID);
#endif
#ifdef XPAR_INTC_0_AXIETHERNET_0_VEC_ID
XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
XIntc_Enable(intcp, XPAR_INTC_0_AXIETHERNET_0_VEC_ID);
#endif
#ifdef XPAR_INTC_0_EMACLITE_0_VEC_ID
#ifdef __MICROBLAZE__
XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
#endif
XIntc_Enable(intcp, XPAR_INTC_0_EMACLITE_0_VEC_ID);
#endif
}
/*
* This function enables interrupts and connects interrupt service routines declared in
* an interrupt vector table
*/
void fnEnableInterrupts(intc *psIntc, const ivt_t *prgsIvt, unsigned int csIVectors)
{
unsigned int isIVector;
Xil_AssertVoid(psIntc != NULL);
Xil_AssertVoid(psIntc->IsReady == XIL_COMPONENT_IS_READY);
/* Hook up interrupt service routines from IVT */
for (isIVector = 0; isIVector < csIVectors; isIVector++)
{
#ifdef __MICROBLAZE__
XIntc_Connect(psIntc, prgsIvt[isIVector].id, prgsIvt[isIVector].handler, prgsIvt[isIVector].pvCallbackRef);
/* Enable the interrupt vector at the interrupt controller */
XIntc_Enable(psIntc, prgsIvt[isIVector].id);
#else
XScuGic_SetPriorityTriggerType(psIntc, prgsIvt[isIVector].id, 0xA0, 0x3);
XScuGic_Connect(psIntc, prgsIvt[isIVector].id, prgsIvt[isIVector].handler, prgsIvt[isIVector].pvCallbackRef);
XScuGic_Enable(psIntc, prgsIvt[isIVector].id);
#endif
}
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler)INTC_HANDLER, psIntc);
Xil_ExceptionEnable();
}
int setup_interrupt()
{
//This functions sets up the interrupt on the ARM
int result;
XScuGic_Config *pCfg = XScuGic_LookupConfig(XPAR_SCUGIC_0_DEVICE_ID);
if (pCfg == NULL){
print("Interrupt Configuration Lookup Failed\n\r");
return XST_FAILURE;
}
result = XScuGic_CfgInitialize(&ScuGic,pCfg,pCfg->CpuBaseAddress);
if(result != XST_SUCCESS){
return result;
}
// self test
result = XScuGic_SelfTest(&ScuGic);
if(result != XST_SUCCESS){
return result;
}
// Initialize the exception handler
Xil_ExceptionInit();
// Register the exception handler
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler)XScuGic_InterruptHandler,&ScuGic);
//Enable the exception handler
Xil_ExceptionEnable();
// Connect the Voice Rec ISR to the exception table
result = XScuGic_Connect(&ScuGic,XPAR_FABRIC_VOICEREC_0_INTERRUPT_INTR,(Xil_InterruptHandler)hls_voicerec_isr,&HlsVoiceRec);
if(result != XST_SUCCESS){
return result;
}
// Enable the Voice Rec ISR
XScuGic_Enable(&ScuGic,XPAR_FABRIC_VOICEREC_0_INTERRUPT_INTR);
return XST_SUCCESS;
}
static int SetupInterruptSystem(XScuGic *GicInstancePtr, XScuTimer *TimerInstancePtr, u16 TimerIntrId)
{
XScuGic_Config *IntcConfig; //GIC config
Xil_ExceptionInit();
//initialise the GIC
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
XScuGic_CfgInitialize(GicInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
//connect to the hardware
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
GicInstancePtr);
//set up the timer interrupt
XScuGic_Connect(GicInstancePtr, TimerIntrId,
(Xil_ExceptionHandler)TimerIntrHandler,
(void *)TimerInstancePtr);
//enable the interrupt for the Timer at GIC
XScuGic_Enable(GicInstancePtr, TimerIntrId);
//enable interrupt on the timer
XScuTimer_EnableInterrupt(TimerInstancePtr);
// Enable interrupts in the Processor.
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
return XST_SUCCESS;
}
int SetupIntrSystem( XScuTimer * TimerInstancePtr,
u16 TimerIntrId)
{
Xil_ExceptionInit();
XScuGic_DeviceInitialize(INTC_DEVICE_ID);
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
(void *)INTC_DEVICE_ID);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
XScuGic_RegisterHandler(INTC_BASE_ADDR,
TimerIntrId,
(Xil_ExceptionHandler)timer_callback,
(void *)&TimerInstance);
/*
* Enable the interrupt for scu timer.
*/
XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, TimerIntrId);
return XST_SUCCESS;
}
static void init_interrupt()
{
Xil_ExceptionInit();
if ((icconf = XScuGic_LookupConfig(XPAR_PS7_SCUGIC_0_DEVICE_ID))
== NULL)
return;
if (XScuGic_CfgInitialize(&ic, icconf, icconf->CpuBaseAddress) !=
XST_SUCCESS)
return;
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler) XScuGic_InterruptHandler, &ic);
if (XScuGic_Connect(&ic, PL_INT_ID, interrupt_handler,
NULL) != XST_SUCCESS)
return;
XScuGic_SetPriorityTriggerType(&ic, PL_INT_ID, 0, /*highest priority*/
3); /* 3 - rising edge, 1 - active high */
XScuGic_Enable(&ic, PL_INT_ID);
Xil_ExceptionEnable();
}
int zynqMP_r5_gic_initialize() {
#ifndef USE_FREERTOS
u32 Status;
XScuGic_Config *IntcConfig; /* The configuration parameters of the interrupt controller */
/*
* Initialize the interrupt controller driver
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(&xInterruptController, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Register the interrupt handler to the hardware interrupt handling
* logic in the ARM processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,&xInterruptController);
Xil_ExceptionEnable();
#endif
OpenAMPInstPtr.IntrID = VRING1_IPI_INTR_VECT;
XScuGic_Connect(&xInterruptController, VRING1_IPI_INTR_VECT,
(Xil_ExceptionHandler)zynqMP_r5_irq_isr,
&OpenAMPInstPtr);
return 0;
}
int SetUpInterruptSystem(XIntc *XIntcInstancePtr)
{
int Status;
Status = XIntc_Connect(XIntcInstancePtr, INTC_DEVICE_INT_ID,
(XInterruptHandler)DeviceDriverHandler,
(void *)0);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = XIntc_Start(XIntcInstancePtr, XIN_SIMULATION_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XIntc_Enable(XIntcInstancePtr, INTC_DEVICE_INT_ID);
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_InterruptHandler,
XIntcInstancePtr);
Xil_ExceptionEnable();
return XST_SUCCESS;
}
/**
*
* This function sets up the interrupt system so interrupts can occur for the
* Uart. This function is application-specific. The user should modify this
* function to fit the application.
*
* @param IntcInstancePtr is a pointer to the instance of the INTC.
* @param UartInstancePtr contains a pointer to the instance of the UART
* driver which is going to be connected to the interrupt
* controller.
* @param UartIntrId is the interrupt Id and is typically
* XPAR_<UARTPS_instance>_INTR value from xparameters.h.
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None.
*
****************************************************************************/
static int SetupInterruptSystem(XScuGic *IntcInstancePtr,
XUartPs *UartInstancePtr,
u16 UartIntrId)
{
int Status;
#ifndef TESTAPP_GEN
XScuGic_Config *IntcConfig; /* Config for interrupt controller */
/*
* Initialize the interrupt controller driver
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the interrupt controller interrupt handler to the
* hardware interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) XScuGic_InterruptHandler,
IntcInstancePtr);
#endif
/*
* Connect a device driver handler that will be called when an
* interrupt for the device occurs, the device driver handler
* performs the specific interrupt processing for the device
*/
Status = XScuGic_Connect(IntcInstancePtr, UartIntrId,
(Xil_ExceptionHandler) XUartPs_InterruptHandler,
(void *) UartInstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupt for the device
*/
XScuGic_Enable(IntcInstancePtr, UartIntrId);
#ifndef TESTAPP_GEN
/*
* Enable interrupts
*/
Xil_ExceptionEnable();
#endif
return XST_SUCCESS;
}
/**
*
* This function setups the interrupt system such that interrupts can occur
* for IIC. This function is application specific since the actual system may
* or may not have an interrupt controller. The IIC device could be directly
* connected to a processor without an interrupt controller. The user should
* modify this function to fit the application.
*
* @param IicPtr contains a pointer to the instance of the IIC component
* which is going to be connected to the interrupt controller.
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @notes None.
*
****************************************************************************/
static int SetupInterruptSystem(XIic *IicPtr)
{
int Status;
/*
* Initialize the interrupt controller driver so that it's ready to use,
* specify the device ID that is generated in xparameters.h
*/
Status = XIntc_Initialize(&InterruptController, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect a device driver handler that will be called when an interrupt
* for the device occurs, the device driver handler performs the
* specific interrupt processing for the device
*/
Status = XIntc_Connect(&InterruptController, INTC_IIC_INTERRUPT_ID,
XIic_InterruptHandler, IicPtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Start the interrupt controller such that interrupts are recognized
* and handled by the processor.
*/
Status = XIntc_Start(&InterruptController, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupts for the IIC device.
*/
XIntc_Enable(&InterruptController, INTC_IIC_INTERRUPT_ID);
/*
* Initialize the exception table.
*/
Xil_ExceptionInit();
/*
* Register the interrupt controller handler with the exception table.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) XIntc_InterruptHandler,
&InterruptController);
/*
* Enable non-critical exceptions.
*/
Xil_ExceptionEnable();
return XST_SUCCESS;
}
/**
*
* This function sets up the interrupt system such that interrupts can occur
* for the USB. This function is application specific since the actual
* system may or may not have an interrupt controller. The USB could be
* directly connected to a processor without an interrupt controller. The
* user should modify this function to fit the application.
*
* @param InstancePtr contains a pointer to the instance of the USB
* component, which is going to be connected to the interrupt
* controller.
*
* @return
* - XST_SUCCESS if successful.
* - XST_FAILURE. if it fails.
*
* @note None
*
*******************************************************************************/
static int SetupInterruptSystem(XUsb * InstancePtr)
{
int Status;
/*
* Initialize the interrupt controller driver.
*/
Status = XIntc_Initialize(&InterruptController, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect a device driver handler that will be called when an interrupt
* for the USB device occurs.
*/
Status = XIntc_Connect(&InterruptController, USB_INTR,
(XInterruptHandler) XUsb_IntrHandler,
(void *) InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Start the interrupt controller such that interrupts are enabled for
* all devices that cause interrupts, specific real mode so that
* the USB can cause interrupts through the interrupt controller.
*/
Status = XIntc_Start(&InterruptController, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Enable the interrupt for the USB.
*/
XIntc_Enable(&InterruptController, USB_INTR);
/*
* Initialize the exception table
*/
Xil_ExceptionInit();
/*
* Register the interrupt controller handler with the exception table
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_InterruptHandler,
&InterruptController);
/*
* Enable non-critical exceptions
*/
Xil_ExceptionEnable();
return XST_SUCCESS;
}
/*
*
* This function setups the interrupt system so interrupts can occur for the
* DMA. This function assumes INTC component exists in the hardware system.
*
* @param AxiDmaPtr is a pointer to the instance of the DMA engine
* @param ReadIntrId is the read channel Interrupt ID.
* @param WriteIntrId is the write channel Interrupt ID.
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None.
*
******************************************************************************/
static int SetupIntrSystem(XAxiVdma *AxiVdmaPtr, u16 ReadIntrId,
u16 WriteIntrId)
{
xil_printf("\r\nEnabling interrupts...");
int Status;
XIntc *IntcInstancePtr = &Intc;
/* Initialize the interrupt controller and connect the ISRs */
// Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
// if (Status != XST_SUCCESS) {
//
// xil_printf( "Failed init intc\r\n");
// return XST_FAILURE;
// }
// Status = XIntc_Connect(IntcInstancePtr, ReadIntrId,
// (XInterruptHandler)XAxiVdma_ReadIntrHandler, AxiVdmaPtr);
// if (Status != XST_SUCCESS) {
//
// xil_printf(
// "Failed read channel connect intc %d\r\n", Status);
// return XST_FAILURE;
// }
Status = XIntc_Connect(IntcInstancePtr, WriteIntrId,
(XInterruptHandler)XAxiVdma_WriteIntrHandler, AxiVdmaPtr);
if (Status != XST_SUCCESS) {
xil_printf(
"Failed write channel connect intc %d\r\n", Status);
return XST_FAILURE;
}
/* Start the interrupt controller */
Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
xil_printf( "Failed to start intc\r\n");
return XST_FAILURE;
}
/* Enable interrupts from the hardware */
// XIntc_Enable(IntcInstancePtr, ReadIntrId);
XIntc_Enable(IntcInstancePtr, WriteIntrId);
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_InterruptHandler,
(void *)IntcInstancePtr);
Xil_ExceptionEnable();
xil_printf("done");
return XST_SUCCESS;
}
/**
* This function setups the interrupt system so interrupts can occur for the
* IIC device. The function is application-specific since the actual system may
* or may not have an interrupt controller. The IIC device could be directly
* connected to a processor without an interrupt controller. The user should
* modify this function to fit the application.
*
* @param IicInstPtr contains a pointer to the instance of the IIC device
* which is going to be connected to the interrupt controller.
*
* @return XST_SUCCESS if successful else XST_FAILURE.
*
* @note None.
*
******************************************************************************/
static int SetupInterruptSystem(XIIC_LIB *I2cLibPtr)
{
int Status;
XIIC *I2cInstancePtr;
INTC *IntcPtr;
I2cInstancePtr = &I2cLibPtr->I2cInstance;
IntcPtr = &I2cLibPtr->IntcInstance;
XScuGic_Config *IntcConfig;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcPtr, IIC_INTR_ID, 0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Status = XScuGic_Connect(IntcPtr, IIC_INTR_ID,
(Xil_InterruptHandler) XIicPs_MasterInterruptHandler,
I2cInstancePtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the IIC device.
*/
XScuGic_Enable(IntcPtr, IIC_INTR_ID);
/*
* Initialize the exception table and register the interrupt
* controller handler with the exception table
*/
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) INTC_HANDLER, IntcPtr);
/* Enable non-critical exceptions */Xil_ExceptionEnable();
return XST_SUCCESS;
}
/**
*
* This function setups the interrupt system such that interrupts can occur
* for the IIC. This function is application specific since the actual
* system may or may not have an interrupt controller. The IIC could be
* directly connected to a processor without an interrupt controller. The
* user should modify this function to fit the application.
*
* @param IicPsPtr contains a pointer to the instance of the Iic
* which is going to be connected to the interrupt controller.
*
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note None.
*
*******************************************************************************/
static int SetupInterruptSystem(XIicPs *IicPsPtr)
{
int Status;
XScuGic_Config *IntcConfig; /* Instance of the interrupt controller */
Xil_ExceptionInit();
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
if (NULL == IntcConfig) {
return XST_FAILURE;
}
Status = XScuGic_CfgInitialize(&InterruptController, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
&InterruptController);
/*
* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device.
*/
Status = XScuGic_Connect(&InterruptController, IIC_INT_VEC_ID,
(Xil_InterruptHandler)XIicPs_MasterInterruptHandler,
(void *)IicPsPtr);
if (Status != XST_SUCCESS) {
return Status;
}
/*
* Enable the interrupt for the Iic device.
*/
XScuGic_Enable(&InterruptController, IIC_INT_VEC_ID);
/*
* Enable interrupts in the Processor.
*/
Xil_ExceptionEnable();
return XST_SUCCESS;
}
int ppc_pit_init( void )
{
// 1. Register Profile_intr_handler as Interrupt handler
// 2. Set PIT Timer Interrupt and Enable it.
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
XTime_PITSetInterval( timer_clk_ticks ) ;
XTime_PITEnableAutoReload() ;
return 0;
}
void prvInitializeExceptions(void)
{
Xil_ExceptionInit();
/*
* Connect the interrupt controller interrupt handler to the hardware
* interrupt handling logic in the ARM processor.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT,
(Xil_ExceptionHandler)FreeRTOS_ExHandler,
(void *)4);
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT,
(Xil_ExceptionHandler)FreeRTOS_ExHandler,
(void *)4);
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT,
(Xil_ExceptionHandler)FreeRTOS_ExHandler,
(void *)8);
}
//--------------------------------------------------------------------
// PowerPC Timer Initialization functions.
// For PowerPC, DEC and opb_timer can be used for Profiling. This
// is selected by the user in standalone BSP
//
//--------------------------------------------------------------------
int powerpc405_init(void)
{
Xil_ExceptionInit();
Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
// Initialize the Timer.
// 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
// 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
#ifdef PPC_PIT_INTERRUPT
ppc_dec_init();
#else
#ifdef TIMER_CONNECT_INTC
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
(Xil_ExceptionHandler)profile_intr_handler,(void *)0);
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
#endif
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
XTime_DECEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
#endif
return 0;
}
//----------------------------------------------------------------------------------------------------//
// @func - hw_init
//! @desc
//! PPC405 hardware specific initialization
//! - Initialize PPC exception handling mechanism
//! - If an interrupt controller is present, register interrupt controller handler
//! as the external interrupt handler.
//! - Register PPC timer interrupt handler as the handler for the PPC PIT interrupt
//! @param
//! - none
//! @return
//! - nothing
//! @note
//! - none
//----------------------------------------------------------------------------------------------------//
void hw_init(void)
{
Xil_ExceptionInit(); // Initialize exception handling
Xil_ExceptionDisable();
#ifdef CONFIG_INTC
int_system_init();
#endif
Xil_ExceptionRegisterHandler(PIT_INT, (Xil_ExceptionHandler)timer_int_handler, (void *)0); // Register PIT interrupt handler
pit_initialize (SYSTMR_INTERVAL); // use SYSTMR_INTERVAL as configured in MSS
}
/**
*
* This function connects the interrupt handler of the IO Module to the
* processor. This function is separate to allow it to be customized for each
* application. Each processor or RTOS may require unique processing to connect
* the interrupt handler.
*
* @param None.
*
* @return None.
*
* @note None.
*
****************************************************************************/
XStatus SetUpInterruptSystem(XIOModule *XIOModuleInstancePtr)
{
XStatus Status;
/*
* Connect a device driver handler that will be called when an interrupt
* for the device occurs, the device driver handler performs the specific
* interrupt processing for the device
*/
Status = XIOModule_Connect(XIOModuleInstancePtr, IOMODULE_DEVICE_ID,
(XInterruptHandler) DeviceDriverHandler,
(void *)0);
if (Status != XST_SUCCESS)
{
return XST_FAILURE;
}
/*
* Start the IO Module such that interrupts are enabled for all devices
* that cause interrupts.
*/
Status = XIOModule_Start(XIOModuleInstancePtr);
if (Status != XST_SUCCESS)
{
return XST_FAILURE;
}
/*
* Enable interrupts for the device and then cause interrupts so the
* handlers will be called.
*/
XIOModule_Enable(XIOModuleInstancePtr, IOMODULE_DEVICE_ID);
/*
* Initialize the exception table.
*/
Xil_ExceptionInit();
/*
* Register the IO module interrupt handler with the exception table.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIOModule_DeviceInterruptHandler,
(void*) 0);
/*
* Enable exceptions.
*/
Xil_ExceptionEnable();
return XST_SUCCESS;
}
int InterruptSystemSetup(XScuGic *XScuGicInstancePtr)
{
// Register GIC interrupt handler
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
XScuGicInstancePtr);
Xil_ExceptionEnable();
return XST_SUCCESS;
}
//--------------------------------------------------------------------
// Initialize the Profile Timer for MicroBlaze Target.
// For MicroBlaze, opb_timer is used. The opb_timer can be directly
// connected to MicroBlaze or connected through Interrupt Controller.
//
//--------------------------------------------------------------------
int microblaze_init(void)
{
// Register profile_intr_handler
// 1. If timer is connected to Interrupt Controller, register the handler
// to Interrupt Controllers vector table.
// 2. If timer is directly connected to MicroBlaze, register the handler
// as Interrupt handler
Xil_ExceptionInit();
#ifdef TIMER_CONNECT_INTC
XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
(XInterruptHandler)profile_intr_handler,(void*)0);
#else
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)profile_intr_handler,
(void *)0) ;
#endif
// Initialize the timer with Timer Ticks
opb_timer_init() ;
// Enable Interrupts in the System, if Profile Timer is the only Interrupt
// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef TIMER_CONNECT_INTC
XIntc_MasterEnable( INTC_BASEADDR );
XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
#endif
#endif
Xil_ExceptionEnable();
return 0;
}
/******************************************************************************
* @brief Initialize Interrupt Controller
*
* @param None.
*
* @return None.
******************************************************************************/
void Ps7IntcInit(void)
{
XScuGic_Config *IntcConfig;
/* Initialize the interrupt controller driver */
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
XScuGic_CfgInitialize(&IntcInstance, IntcConfig, IntcConfig->CpuBaseAddress);
Xil_ExceptionInit();
/* Connect the interrupt controller interrupt handler to the hardware interrupt logic */
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, &IntcInstance);
}
/**
* This function sets up the interrupt system for the example. The processing
* contained in this function assumes the hardware system was built with
* and interrupt controller.
*
* @param None.
*
* @return A status indicating XST_SUCCESS or a value that is contained in
* xstatus.h.
*
* @note None.
*
*****************************************************************************/
int zed_ali3_controller_demo_SetupInterruptSystem(zed_ali3_controller_demo_t *pDemo)
{
int Result;
/*
* Initialize the interrupt controller driver so that it is ready to
* use.
*/
pDemo->pIntcConfig = XScuGic_LookupConfig(pDemo->uDeviceId_IRQ_Touch);
if (NULL == pDemo->pIntcConfig) {
return XST_FAILURE;
}
Result = XScuGic_CfgInitialize(&(pDemo->Intc), pDemo->pIntcConfig,
pDemo->pIntcConfig->CpuBaseAddress);
if (Result != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch,
0xA0, 0x3);
/*
* Connect the interrupt handler that will be called when an
* interrupt occurs for the device.
*/
Result = XScuGic_Connect(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch,
(Xil_ExceptionHandler)TouchIsr, pDemo);
if (Result != XST_SUCCESS) {
return Result;
}
/*
* Enable the PS interrupts for the touch controller hardware device.
*/
XScuGic_Enable(&(pDemo->Intc), pDemo->uInterruptId_IRQ_Touch);
/*
* Initialize the exception table and register the interrupt
* controller handler with the exception table
*/
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler, &(pDemo->Intc));
/* Enable non-critical exceptions */
Xil_ExceptionEnable();
return XST_SUCCESS;
}
