/**************************************************************************** * * Invalidate a Data cache line. If the byte specified by the address (adr) * is cached by the Data cache, the cacheline containing that byte is * invalidated. If the cacheline is modified (dirty), the modified contents * are lost and are NOT written to system memory before the line is * invalidated. * * @param Address to be flushed. * * @return None. * * @note The bottom 4 bits are set to 0, forced by architecture. * ****************************************************************************/ void Xil_DCacheInvalidateLine(u32 adr) { u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); Xil_L2CacheInvalidateLine(adr); Xil_L1DCacheInvalidateLine(adr); mtcpsr(currmask); }
/**************************************************************************** * * Invalidate a Data cache line. If the byte specified by the address (adr) * is cached by the Data cache, the cacheline containing that byte is * invalidated. If the cacheline is modified (dirty), the modified contents * are lost and are NOT written to system memory before the line is * invalidated. * * @param Address to be flushed. * * @return None. * * @note The bottom 4 bits are set to 0, forced by architecture. * ****************************************************************************/ void Xil_DCacheInvalidateLine(u32 adr) { u32 currmask; currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); #ifndef USE_AMP Xil_L2CacheInvalidateLine(adr); #endif Xil_L1DCacheInvalidateLine(adr); mtcpsr(currmask); }