static void __ip22zilog_reset(struct uart_ip22zilog_port *up)
{
struct zilog_channel *channel;
int i;
if (up->flags & IP22ZILOG_FLAG_RESET_DONE)
return;
/* Let pending transmits finish. */
channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
for (i = 0; i < 1000; i++) {
unsigned char stat = read_zsreg(channel, R1);
if (stat & ALL_SNT)
break;
udelay(100);
}
if (!ZS_IS_CHANNEL_A(up)) {
up++;
channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
}
write_zsreg(channel, R9, FHWRES);
ZSDELAY_LONG();
(void) read_zsreg(channel, R0);
up->flags |= IP22ZILOG_FLAG_RESET_DONE;
up->next->flags |= IP22ZILOG_FLAG_RESET_DONE;
}
static void __init ip22zilog_init_hw(void)
{
int i;
for (i = 0; i < NUM_CHANNELS; i++) {
struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
unsigned long flags;
int baud, brg;
spin_lock_irqsave(&up->port.lock, flags);
if (ZS_IS_CHANNEL_A(up)) {
write_zsreg(channel, R9, FHWRES);
ZSDELAY_LONG();
(void) read_zsreg(channel, R0);
}
/* Normal serial TTY. */
up->parity_mask = 0xff;
up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
up->curregs[R3] = RxENAB | Rx8;
up->curregs[R5] = TxENAB | Tx8;
up->curregs[R9] = NV | MIE;
up->curregs[R10] = NRZ;
up->curregs[R11] = TCBR | RCBR;
baud = 9600;
brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
up->curregs[R12] = (brg & 0xff);
up->curregs[R13] = (brg >> 8) & 0xff;
up->curregs[R14] = BRENAB;
__load_zsregs(channel, up->curregs);
/* set master interrupt enable */
write_zsreg(channel, R9, up->curregs[R9]);
spin_unlock_irqrestore(&up->port.lock, flags);
}
}
