static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
{
unsigned long timeout = jiffies + HZ*1;
/* wait for stop */
show_state(i2c);
while (time_before(jiffies, timeout)) {
if (i2c_debug > 1)
dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
__func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
(readl(_ISR(i2c)) & ISR_SAD) != 0 ||
(readl(_ICR(i2c)) & ICR_SCLE) == 0) {
if (i2c_debug > 1)
dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
return 1;
}
msleep(1);
}
if (i2c_debug > 0)
dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
return 0;
}
static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
{
unsigned long timeout = jiffies + HZ*4;
while (time_before(jiffies, timeout)) {
if (i2c_debug > 1)
dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
__func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
if (readl(_ISR(i2c)) & ISR_SAD) {
if (i2c_debug > 0)
dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
goto out;
}
/* wait for unit and bus being not busy, and we also do a
* quick check of the i2c lines themselves to ensure they've
* gone high...
*/
if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
if (i2c_debug > 0)
dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
return 1;
}
msleep(1);
}
if (i2c_debug > 0)
dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
out:
return 0;
}
void ezx_i2c_pm_resume(void)
{
/* enable clocks */
CKEN |= CKEN14_I2C;
set_GPIO_mode(117 | GPIO_ALT_FN_1_IN);
set_GPIO_mode(118 | GPIO_ALT_FN_1_IN);
/* enable irqs */
enable_irq(i2c_pxa_data.irq);
/* disable unit */
_ICR(adap) &= ~ICR_IUE;
/* reset the unit */
_ICR(adap) |= ICR_UR;
udelay(100);
_ICR(adap) |= ICR_FM;
/* disable unit */
_ICR(adap) &= ~ICR_IUE;
/* XXX: I2C_PXA_SLAVE_ADDR == I2C_PXA_PWR_SLAVE_ADDR ??? */
/* set our slave address */
_ISAR(adap) = I2C_PXA_SLAVE_ADDR;
/* set control register values */
_ICR(adap) = I2C_ICR_INIT;
/* set clear interrupt bits */
_ISR(adap) = I2C_ISR_INIT;
/* enable unit */
_ICR(adap) |= ICR_IUE;
udelay(100);
}
static void i2c_pxa_reset(struct pxa_i2c *i2c)
{
pr_debug("Resetting I2C Controller Unit\n");
/* abort any transfer currently under way */
i2c_pxa_abort(i2c);
/* reset according to 9.8 */
writel(ICR_UR, _ICR(i2c));
writel(I2C_ISR_INIT, _ISR(i2c));
writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
writel(i2c->slave_addr, _ISAR(i2c));
/* set control register values */
writel(I2C_ICR_INIT, _ICR(i2c));
#ifdef CONFIG_I2C_PXA_SLAVE
dev_info(&i2c->adap.dev, "Enabling slave mode\n");
writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
#endif
i2c_pxa_set_slave(i2c, 0);
/* enable unit */
writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
udelay(100);
}
/*
* clear the hold on the bus, and take of anything else
* that has been configured
*/
static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
{
show_state(i2c);
if (errcode < 0) {
udelay(100); /* simple delay */
} else {
/* we need to wait for the stop condition to end */
/* if we where in stop, then clear... */
if (readl(_ICR(i2c)) & ICR_STOP) {
udelay(100);
writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
}
if (!i2c_pxa_wait_slave(i2c)) {
dev_err(&i2c->adap.dev, "%s: wait timedout\n",
__func__);
return;
}
}
writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
if (i2c_debug) {
dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
decode_ICR(readl(_ICR(i2c)));
}
}
static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
{
int timeout = DEF_TIMEOUT;
while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
timeout += 4;
msleep(2);
show_state(i2c);
}
if (timeout <= 0)
show_state(i2c);
return timeout <= 0 ? I2C_RETRY : 0;
}
static int i2c_pxa_wait_bus_not_busy(struct i2c_algo_pxa_data *adap)
{
int timeout = DEF_TIMEOUT;
while (timeout-- && (_ISR(adap) & ISR_IBB)) {
udelay(100); /* wait for 100 us */
}
return (timeout<=0);
}
static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
{
struct pxa_i2c *i2c = dev_id;
u32 isr = readl(_ISR(i2c));
if (i2c_debug > 2 && 0) {
dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
__func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
decode_ISR(isr);
}
if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
i2c->isrlog[i2c->irqlogidx++] = isr;
show_state(i2c);
/*
* Always clear all pending IRQs.
*/
writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
if (isr & ISR_SAD)
i2c_pxa_slave_start(i2c, isr);
if (isr & ISR_SSD)
i2c_pxa_slave_stop(i2c);
if (i2c_pxa_is_slavemode(i2c)) {
if (isr & ISR_ITE)
i2c_pxa_slave_txempty(i2c, isr);
if (isr & ISR_IRF)
i2c_pxa_slave_rxfull(i2c, isr);
} else if (i2c->msg) {
if (isr & ISR_ITE)
i2c_pxa_irq_txempty(i2c, isr);
if (isr & ISR_IRF)
i2c_pxa_irq_rxfull(i2c, isr);
} else {
i2c_pxa_scream_blue_murder(i2c, "spurious irq");
}
return IRQ_HANDLED;
}
static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
{
unsigned int i;
printk("i2c: error: %s\n", why);
printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
printk("i2c: ICR: %08x ISR: %08x\n"
"i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c)));
for (i = 0; i < i2c->irqlogidx; i++)
printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
printk("\n");
}
static void i2c_pxa_handler(int this_irq, void *dev_id, struct pt_regs *regs)
{
int status;
struct i2c_algo_pxa_data *adap = &i2c_pxa_data;
status = (_ISR(adap));
if (status & ISR_BED){
(_ISR(adap)) |= ISR_BED;
adap->bus_error = ISR_BED;
}
if (status & ISR_ITE){
(_ISR(adap)) |= ISR_ITE;
adap->tx_finished=ISR_ITE;
}
if (status & ISR_IRF){
(_ISR(adap)) |= ISR_IRF;
adap->rx_finished=ISR_IRF;
}
adap->i2c_pending = 1;
wake_up_interruptible(&adap->i2c_wait);
}
static int i2c_pxa_set_master(struct pxa_i2c *i2c)
{
if (i2c_debug)
dev_dbg(&i2c->adap.dev, "setting to bus master\n");
if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
if (!i2c_pxa_wait_master(i2c)) {
dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
return I2C_RETRY;
}
}
writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
return 0;
}
static void i2c_pxa_reset(struct i2c_algo_pxa_data *adap)
{
/* set the global I2C clocks on */
CKEN |= CKEN14_I2C;
set_GPIO_mode(117 | GPIO_ALT_FN_1_IN);
set_GPIO_mode(118 | GPIO_ALT_FN_1_IN);
#ifdef CONFIG_POWER_I2C
/* set the global PWR_I2C clock on */
CKEN |= CKEN15_PWRI2C;
/* Enable PI2C controller PWR_SCL and PWR_SDA */
PCFR |= PCFR_PI2CEN;
/* Setup GPIO3 and GPIO4 to ALT_FN1_IN (PWR_SCL and PWR_SDA) */
set_GPIO_mode(3 | GPIO_ALT_FN_1_IN);
set_GPIO_mode(4 | GPIO_ALT_FN_1_IN);
#endif
/* disable unit */
_ICR(adap) &= ~ICR_IUE;
/* reset the unit */
_ICR(adap) |= ICR_UR;
udelay(100);
_ICR(adap) |= ICR_FM;
/* disable unit */
_ICR(adap) &= ~ICR_IUE;
/* XXX: I2C_PXA_SLAVE_ADDR == I2C_PXA_PWR_SLAVE_ADDR ??? */
/* set our slave address */
_ISAR(adap) = I2C_PXA_SLAVE_ADDR;
/* set control register values */
_ICR(adap) = I2C_ICR_INIT;
/* set clear interrupt bits */
_ISR(adap) = I2C_ISR_INIT;
/* enable unit */
_ICR(adap) |= ICR_IUE;
udelay(100);
}
static int ezx_i2c_pm_callback(struct pm_dev *pm_dev, pm_request_t req, void *data)
{
switch(req)
{
case PM_SUSPEND:
/* disable IRQs */
if (i2c_pxa_data.irq)
disable_irq(i2c_pxa_data.irq);
/* disable PI2C Controller */
PCFR &= ~PCFR_PI2CEN;
/* disable clocks */
CKEN &= ~CKEN14_I2C;
#ifdef CONFIG_POWER_I2C
if (i2c_pxa_pwr_data.irq)
disable_irq(i2c_pxa_pwr_data.irq);
/* disable PI2C Controller */
PCFR &= ~PCFR_PI2CEN;
CKEN &= ~CKEN15_PWRI2C;
#endif
break;
case PM_RESUME:
/* enable clocks */
CKEN |= CKEN14_I2C;
set_GPIO_mode(117 | GPIO_ALT_FN_1_IN);
set_GPIO_mode(118 | GPIO_ALT_FN_1_IN);
/* enable irqs */
enable_irq(i2c_pxa_data.irq);
#ifdef CONFIG_POWER_I2C
/* set the global PWR_I2C clock on */
CKEN |= CKEN15_PWRI2C;
/* Enable PI2C controller PWR_SCL and PWR_SDA */
PCFR |= PCFR_PI2CEN;
set_GPIO_mode(3 | GPIO_ALT_FN_1_IN);
set_GPIO_mode(4 | GPIO_ALT_FN_1_IN);
enable_irq(i2c_pxa_pwr_data.irq);
#endif
/* disable unit */
_ICR(adap) &= ~ICR_IUE;
/* reset the unit */
_ICR(adap) |= ICR_UR;
udelay(100);
_ICR(adap) |= ICR_FM;
/* disable unit */
_ICR(adap) &= ~ICR_IUE;
/* XXX: I2C_PXA_SLAVE_ADDR == I2C_PXA_PWR_SLAVE_ADDR ??? */
/* set our slave address */
_ISAR(adap) = I2C_PXA_SLAVE_ADDR;
/* set control register values */
_ICR(adap) = I2C_ICR_INIT;
/* set clear interrupt bits */
_ISR(adap) = I2C_ISR_INIT;
/* enable unit */
_ICR(adap) |= ICR_IUE;
udelay(100);
break;
}
return 0;
}
static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
{
dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
}
