static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct krait_mux_clk *mux = to_krait_mux_clk(hw);
u32 sel;
sel = clk_mux_reindex(index, mux->parent_map, 0);
mux->en_mask = sel;
/* Don't touch mux if CPU is off as it won't work */
if (__clk_is_enabled(hw->clk))
__krait_mux_set_sel(mux, sel);
return 0;
}
static int __init sunxi_clk_default_sdm(void)
{
#ifdef SYS_CONFIG_PAT_EN
struct clk *clk = NULL;
script_item_u script_item;
struct sunxi_clk_factors *factor=NULL;
int i;
unsigned long reg;
for(i=0;i<sizeof(clkpat_table)/sizeof(struct sunxi_clk_pat_item);i++)
{
if((script_get_item("clock", clkpat_table[i].patname, &script_item) == SCIRPT_ITEM_VALUE_TYPE_INT))
{
clk = clk_get(NULL,clkpat_table[i].name);
if(!IS_ERR_OR_NULL(clk))
{
factor = to_clk_factor(clk->hw);
if(script_item.val)
{
factor->config->sdmwidth = 1;
#ifdef SYS_CONFIG_PAT_VAL
if(script_item.val != 1) //avoid old format usage to only enable
factor->config->sdmval=script_item.val;
#endif
//sync with already enable PLLs
if (clk->enable_count && __clk_is_enabled(clk))
{
reg = readl(factor->reg);
writel(factor->config->sdmval, (void __iomem *)factor->config->sdmpat);
reg = SET_BITS(factor->config->sdmshift, factor->config->sdmwidth, reg, 1);
writel(reg, factor->reg);
}
}
else
factor->config->sdmwidth = 0;
clk_put(clk);
clk=NULL;
}
}
}
#endif
return 0;
}
int gpu_is_clock_on(void)
{
return __clk_is_enabled(aclk_g3d);
}
int gpu_is_clock_on(void)
{
#if 0
return __clk_is_enabled(aclk_g3d);
#endif
}
static int fimg2d4x_get_clk_cnt(struct clk *clk)
{
return __clk_is_enabled(clk);
}