static int _arc_v2_irq_unit_resume(struct device *dev)
{
u8_t irq;
u32_t status32;
ARG_UNUSED(dev);
/* Interrupts from 0 to 15 are exceptions and they are ignored
* by IRQ auxiliary registers. For that reason we skip those
* values in this loop.
*/
for (irq = 16; irq < CONFIG_NUM_IRQS; irq++) {
_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
_arc_v2_aux_reg_write(_ARC_V2_IRQ_PRIORITY,
ctx.irq_config[irq - 16] >> 2);
_arc_v2_aux_reg_write(_ARC_V2_IRQ_TRIGGER,
(ctx.irq_config[irq - 16] >> 1) & BIT(0));
_arc_v2_aux_reg_write(_ARC_V2_IRQ_ENABLE,
ctx.irq_config[irq - 16] & BIT(0));
}
_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_CTRL, ctx.irq_ctrl);
_arc_v2_aux_reg_write(_ARC_V2_IRQ_VECT_BASE, ctx.irq_vect_base);
status32 = _arc_v2_aux_reg_read(_ARC_V2_STATUS32);
status32 |= _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL);
__builtin_arc_kflag(status32);
_arc_v2_irq_unit_device_power_state = DEVICE_PM_ACTIVE_STATE;
return 0;
}
void _arc_v2_irq_unit_init(void)
{
int irq; /* the interrupt index */
for (irq = 16; irq < CONFIG_NUM_IRQS; irq++) {
_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
_arc_v2_aux_reg_write(_ARC_V2_IRQ_PRIORITY, 1);
_arc_v2_aux_reg_write(_ARC_V2_IRQ_ENABLE, _ARC_V2_INT_DISABLE);
_arc_v2_aux_reg_write(_ARC_V2_IRQ_TRIGGER, _ARC_V2_INT_LEVEL);
}
}
static void disable_icache(void)
{
unsigned int val;
val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
val &= 0xff; /* version field */
if (val == 0) {
return; /* skip if i-cache is not present */
}
_arc_v2_aux_reg_write(_ARC_V2_IC_IVIC, 0);
__asm__ __volatile__ ("nop");
_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, 1);
}
static inline void _i2c_qse_ss_reg_write(struct device *dev,
uint32_t reg, uint32_t val)
{
struct i2c_qse_ss_rom_config * const rom = dev->config->config_info;
_arc_v2_aux_reg_write(rom->base_address + reg, val);
}
static int _arc_v2_irq_unit_suspend(struct device *dev)
{
u8_t irq;
ARG_UNUSED(dev);
/* Interrupts from 0 to 15 are exceptions and they are ignored
* by IRQ auxiliary registers. For that reason we skip those
* values in this loop.
*/
for (irq = 16; irq < CONFIG_NUM_IRQS; irq++) {
_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
ctx.irq_config[irq - 16] =
_arc_v2_aux_reg_read(_ARC_V2_IRQ_PRIORITY) << 2;
ctx.irq_config[irq - 16] |=
_arc_v2_aux_reg_read(_ARC_V2_IRQ_TRIGGER) << 1;
ctx.irq_config[irq - 16] |=
_arc_v2_aux_reg_read(_ARC_V2_IRQ_ENABLE);
}
ctx.irq_ctrl = _arc_v2_aux_reg_read(_ARC_V2_AUX_IRQ_CTRL);
ctx.irq_vect_base = _arc_v2_aux_reg_read(_ARC_V2_IRQ_VECT_BASE);
_arc_v2_irq_unit_device_power_state = DEVICE_PM_SUSPEND_STATE;
return 0;
}
/*
* @brief Output a character to serial port
*
* @param dev UART device struct
* @param c character to output
*/
unsigned char uart_nsim_poll_out(struct device *dev, unsigned char c)
{
/* wait for transmitter to ready to accept a character */
while ((_arc_v2_aux_reg_read(STATUS_REG(dev)) & TXEMPTY) == 0)
;
_arc_v2_aux_reg_write(DATA_REG(dev), c);
return c;
}
/*
* @brief Output a character to serial port
* @port: port number
* @c: character to output
*/
unsigned char uart_poll_out(int port, unsigned char c)
{
/* wait for transmitter to ready to accept a character */
while ((_arc_v2_aux_reg_read(STATUS_REG(port)) & TXEMPTY) == 0)
;
_arc_v2_aux_reg_write(DATA_REG(port), c);
return c;
}
static int _arc_v2_irq_unit_init(struct device *unused)
{
ARG_UNUSED(unused);
int irq; /* the interrupt index */
/* Interrupts from 0 to 15 are exceptions and they are ignored
* by IRQ auxiliary registers. For that reason we skip those
* values in this loop.
*/
for (irq = 16; irq < CONFIG_NUM_IRQS; irq++) {
_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
_arc_v2_aux_reg_write(_ARC_V2_IRQ_PRIORITY,
(CONFIG_NUM_IRQ_PRIO_LEVELS-1)); /* lowest priority */
_arc_v2_aux_reg_write(_ARC_V2_IRQ_ENABLE, _ARC_V2_INT_DISABLE);
_arc_v2_aux_reg_write(_ARC_V2_IRQ_TRIGGER, _ARC_V2_INT_LEVEL);
}
return 0;
}
static void invalidate_dcache(void)
{
unsigned int val;
val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
val &= 0xff; /* version field */
if (val == 0) {
return; /* skip if d-cache is not present */
}
_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
}
void dw_ss_adc_err_ISR_proc(struct device *dev)
{
struct adc_config *config = dev->config->config_info;
struct adc_info *info = dev->driver_data;
uint32_t adc_base = config->reg_base;
uint32_t reg_val = _arc_v2_aux_reg_read(adc_base + ADC_SET);
_arc_v2_aux_reg_write( adc_base + ADC_CTRL,
ADC_INT_DSB|ADC_CLK_ENABLE|ADC_SEQ_PTR_RST);
_arc_v2_aux_reg_write( adc_base + ADC_CTRL,
reg_val | ADC_FLUSH_RX);
info->state = ADC_STATE_IDLE;
_arc_v2_aux_reg_write( adc_base +ADC_CTRL,
ADC_INT_DSB|ADC_CLK_ENABLE|ADC_CLR_OVERFLOW|ADC_CLR_UNDRFLOW);
if (likely( NULL != info->err_cb))
{
info->err_cb( dev );
}
}
static void adjust_vector_table_base(void)
{
extern struct vector_table _VectorTable;
unsigned int vbr;
/* if the compiled-in vector table is different
* from the base address known by the ARC CPU,
* set the vector base to the compiled-in address.
*/
vbr = _arc_v2_aux_reg_read(_ARC_V2_IRQ_VECT_BASE);
vbr &= 0xfffffc00;
if (vbr != (unsigned int)&_VectorTable) {
_arc_v2_aux_reg_write(_ARC_V2_IRQ_VECT_BASE,
(unsigned int)&_VectorTable);
}
}
void _sys_soc_power_state_post_ops(enum power_states state)
{
u32_t limit;
switch (state) {
case SYS_POWER_STATE_CPU_LPS_1:
/* Expire the timer as it is disabled in SS2. */
limit = _arc_v2_aux_reg_read(_ARC_V2_TMR0_LIMIT);
_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, limit - 1);
case SYS_POWER_STATE_CPU_LPS:
__builtin_arc_seti(0);
break;
case SYS_POWER_STATE_DEEP_SLEEP:
qm_ss_power_soc_lpss_disable();
/* If flag is cleared it means the system entered in
* sleep state while we were in LPS. In that case, we
* must set ARC_READY flag so x86 core can continue
* its execution.
*/
if ((QM_SCSS_GP->gp0 & GP0_BIT_SLEEP_READY) == 0) {
_quark_se_ss_ready();
__builtin_arc_seti(0);
} else {
QM_SCSS_GP->gp0 &= ~GP0_BIT_SLEEP_READY;
QM_SCSS_GP->gps0 &= ~QM_GPS0_BIT_SENSOR_WAKEUP;
}
break;
case SYS_POWER_STATE_DEEP_SLEEP_1:
case SYS_POWER_STATE_DEEP_SLEEP_2:
/* Route RTC interrupt to the current core */
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->rtc_0_int_mask);
__builtin_arc_seti(0);
break;
break;
default:
break;
}
}
void _arc_v2_irq_unit_trigger_set(int irq, unsigned int trigger)
{
_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
_arc_v2_aux_reg_write(_ARC_V2_IRQ_TRIGGER, trigger);
}
void _arc_v2_irq_unit_int_eoi(int irq)
{
_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
_arc_v2_aux_reg_write(_ARC_V2_IRQ_PULSE_CANCEL, 1);
}
/**
*
* @brief Set Timer0 limit register to the specified value
*
* @return N/A
*/
static ALWAYS_INLINE void timer0_limit_register_set(u32_t count)
{
_arc_v2_aux_reg_write(_ARC_V2_TMR0_LIMIT, count);
}
/**
*
* @brief Set Timer0 control register to the specified value
*
* @return N/A
*/
static ALWAYS_INLINE void timer0_control_register_set(u32_t value)
{
_arc_v2_aux_reg_write(_ARC_V2_TMR0_CONTROL, value);
}
/**
*
* @brief Set Timer0 count register to the specified value
*
* @return N/A
*/
static ALWAYS_INLINE void timer0_count_register_set(u32_t value)
{
_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, value);
}
void dw_ss_adc_rx_ISR_proc(struct device *dev)
{
struct adc_config *config;
struct device_config *dev_config;
struct adc_info *info;
uint32_t adc_base;
uint32_t i, reg_val, rx_cnt;
uint32_t rd = 0;
uint32_t idx;
dev_config = dev->config;
config = dev_config->config_info;
info = dev->driver_data;
adc_base = config->reg_base;
idx = info->index;
if (IO_ADC_SEQ_MODE_REPETITIVE == config->seq_mode)
{
if (NULL == info->rx_buf[idx])
{
goto cli;
}
rx_cnt = (config->fifo_tld + 1);
}
else
{
rx_cnt = info->seq_size;
}
if (rx_cnt > info->rx_len)
{
rx_cnt = info->rx_len;
}
for (i = 0; i < rx_cnt; i++)
{
reg_val = _arc_v2_aux_reg_read( adc_base + ADC_SET );
_arc_v2_aux_reg_write( adc_base + ADC_SET,
reg_val|ADC_POP_SAMPLE);
rd = _arc_v2_aux_reg_read( adc_base + ADC_SAMPLE );
info->rx_buf[idx][i] = rd;
}
info->rx_buf[idx] += i;
info->rx_len -= i;
if (0 == info->rx_len)
{
if (likely( NULL != info->rx_cb))
{
info->rx_cb(dev);
}
if (IO_ADC_SEQ_MODE_SINGLESHOT == config->seq_mode)
{
_arc_v2_aux_reg_write( adc_base + ADC_CTRL,
ADC_INT_DSB|ADC_CLK_ENABLE|ADC_SEQ_PTR_RST);
reg_val = _arc_v2_aux_reg_read( adc_base + ADC_SET );
_arc_v2_aux_reg_write( adc_base + ADC_SET,
reg_val | ADC_FLUSH_RX);
info->state = ADC_STATE_IDLE;
goto cli;
}
info->rx_buf[idx] = NULL;
idx++;
idx %= BUFS_NUM;
info->index = idx;
}
else if (IO_ADC_SEQ_MODE_SINGLESHOT == config->seq_mode)
{
_arc_v2_aux_reg_write( adc_base + ADC_CTRL,
ADC_INT_DSB|ADC_CLK_ENABLE|ADC_SEQ_PTR_RST);
info->state = ADC_STATE_IDLE;
if (likely( NULL != info->rx_cb))
{
info->rx_cb(dev);
}
}
cli:
reg_val = _arc_v2_aux_reg_read( adc_base + ADC_CTRL );
_arc_v2_aux_reg_write( adc_base + ADC_CTRL,
reg_val | ADC_CLR_DATA_A);
}
unsigned int _arc_v2_irq_unit_trigger_get(int irq)
{
_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
return _arc_v2_aux_reg_read(_ARC_V2_IRQ_TRIGGER);
}
