void init_hardware(void)
{
#if PE_LDD_VERSION
/* Watch Dog disabled by CPU bean (need to setup in CPU Inspector) */
__pe_initialize_hardware();
#else
_bsp_initialize_hardware();
#endif
/* Enable pin clocks */
_bsp_gpio_io_init ();
/* Initialize FlexBus */
_bsp_flexbus_setup();
/* Initialize MRAM */
_bsp_flexbus_mram_setup((uint_32)BSP_EXTERNAL_MRAM_RAM_BASE);
}
void init_hardware(void)
{
#if PE_LDD_VERSION
/* Watch Dog disabled by CPU bean (need to setup in CPU Inspector) */
__pe_initialize_hardware();
#else
_bsp_initialize_hardware();
#endif
/* Enable pin clocks */
_bsp_gpio_io_init ();
/* Initialize FlexBus */
_bsp_flexbus_setup();
}
void init_hardware(void)
{
#if MQX_ENABLE_LOW_POWER
/* Reset from LLWU wake up source */
if (_lpm_get_reset_source() == MQX_RESET_SOURCE_LLWU)
{
PMC_REGSC |= PMC_REGSC_ACKISO_MASK;
}
#endif
#if PE_LDD_VERSION
/* Watch Dog disabled by CPU bean (need to setup in CPU Inspector) */
__pe_initialize_hardware();
#else
_bsp_initialize_hardware();
#endif
/* Enable pin clocks */
_bsp_gpio_io_init ();
/* Initialize FlexBus */
_bsp_flexbus_setup();
}
void kinetis_init(void)
{
#if PE_LDD_VERSION
/* Watchdog disabled by CPU bean (need to setup in CPU Inspector) */
__pe_initialize_hardware();
/* Enable clock to peripheral modules */
kinetis_clock_enable();
_bsp_mpu_disable();
/*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/
PE_low_level_init();
#else
kinetis_wdt_disable();
pll_init();
/* Enable clock to peripheral modules */
kinetis_clock_enable();
_bsp_mpu_disable();
#endif
/* Initialize FlexBus */
_bsp_flexbus_setup();
/* Initialize MRAM */
_bsp_flexbus_mram_setup((uint_32)BSP_EXTERNAL_MRAM_RAM_BASE);
}
void mcf5225_init
(
void
)
{
VMCF5225_STRUCT_PTR reg_ptr = (VMCF5225_STRUCT_PTR)BSP_IPSBAR;
uint_8 tmp_8[2];
uint_32 i;
/* Disable Software Watchdog Timer */
reg_ptr->SCM.CWCR = 0;
/* Enable Program Status Outputs, PST[3:0] signals */
reg_ptr->GPIO.PDDPAR = MCF5225_GPIO_PDDPAR_PST;
/* Initialize the PLL
** Divide 48Mhz reference crystal by 6 and multiply by 10 to achieve a
** system clock of 80 Mhz.
**
** To set an MFD of ‘x’ and an RFD of ‘y’, you must first program RFD to ‘y+1’,
** then program MFD to ‘x’, then let the PLL lock, then program RFD to ‘y’. If
** you program RFD simultaneous to MFD, you may over-clock and damage the part.
*/
reg_ptr->CLK.OCLR = 0xf0;
reg_ptr->CLK.CCHR = 5;
reg_ptr->CLK.SYNCR = 0 |
MCF5225_CLOCK_SYNCR_RFD(0) |
MCF5225_CLOCK_SYNCR_MFD(3) |
MCF5225_CLOCK_SYNCR_PLLMODE|
MCF5225_CLOCK_SYNCR_PLLEN;
/* wait for PLL locks before switching clock source */
while (!(reg_ptr->CLK.SYNSR & MCF5225_CLOCK_SYNSR_LOCK)) {}
/* now changing clock source is possible */
reg_ptr->CLK.CCLR = 0;
reg_ptr->CLK.SYNCR |= MCF5225_CLOCK_SYNCR_CLKSRC;
/* wait for PLL lock again */
while (!(reg_ptr->CLK.SYNSR & MCF5225_CLOCK_SYNSR_LOCK)) {}
/* Enable on-chip modules to access internal SRAM */
reg_ptr->SCM.RAMBAR = MCF5225_SCM_RAMBAR_BA((uint_32)__INTERNAL_SRAM_BASE) | MCF5225_SCM_RAMBAR_BDE;
/* init flexbus */
_bsp_flexbus_setup();
/* init MRAM */
_bsp_flexbus_mram_setup((uint_32)BSP_EXTERNAL_MRAM_BASE);
/* Workarround for not problematic PHY reset */
tmp_8[0] = reg_ptr->GPIO.PTIPAR; // save current state
tmp_8[1] = reg_ptr->GPIO.PTJPAR; // save current state
reg_ptr->GPIO.PTIPAR = 0x00; // Ethernet signals now GPIO
reg_ptr->GPIO.PTJPAR = 0x00; // Ethernet signals now GPIO
reg_ptr->GPIO.DDRTI = 0xFF; // GPIO output
reg_ptr->GPIO.DDRTJ = 0xFF; // GPIO output
reg_ptr->GPIO.PORTTI = 0x00; // force Ethernet signals low
reg_ptr->GPIO.PORTTJ = 0x00; // force Ethernet signals low
reg_ptr->CCM.RCR |= MCF5225_CCM_RCR_FRCRSTOUT; // assert RSTO
for (i = 0; i < 10000; i++)
_ASM_NOP();
reg_ptr->CCM.RCR &= ~(MCF5225_CCM_RCR_FRCRSTOUT); // negate RSTO
for (i = 0; i < 1000000; i++)
_ASM_NOP();
reg_ptr->GPIO.PTIPAR = tmp_8[0]; // restore current state
reg_ptr->GPIO.PTJPAR = tmp_8[1]; // restore Ethernet signals low
}
