void recMTSAB( void ) { if( GPR_IS_CONST1(_Rs_) ) { MOV32ItoM((uptr)&cpuRegs.sa, ((g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)) ); } else { _eeMoveGPRtoR(EAX, _Rs_); AND32ItoR(EAX, 0xF); XOR32ItoR(EAX, _Imm_&0xf); MOV32RtoM((uptr)&cpuRegs.sa, EAX); } }
void recMTSAB() { if( GPR_IS_CONST1(_Rs_) ) { xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)) ); } else { _eeMoveGPRtoR(eax, _Rs_); xAND(eax, 0xF); xXOR(eax, _Imm_&0xf); xMOV(ptr[&cpuRegs.sa], eax); } }
void recMTC0() { if( GPR_IS_CONST1(_Rt_) ) { switch (_Rd_) { case 12: iFlushCall(FLUSH_INTERPRETER); xFastCall(WriteCP0Status, g_cpuConstRegs[_Rt_].UL[0] ); break; case 9: xMOV(ecx, ptr[&cpuRegs.cycle]); xMOV(ptr[&s_iLastCOP0Cycle], ecx); xMOV(ptr32[&cpuRegs.CP0.r[9]], g_cpuConstRegs[_Rt_].UL[0]); break; case 25: switch(_Imm_ & 0x3F) { case 0: iFlushCall(FLUSH_INTERPRETER); xFastCall(COP0_UpdatePCCR ); xMOV( ptr32[&cpuRegs.PERF.n.pccr], g_cpuConstRegs[_Rt_].UL[0] ); xFastCall(COP0_DiagnosticPCCR ); break; case 1: xMOV(eax, ptr[&cpuRegs.cycle]); xMOV(ptr32[&cpuRegs.PERF.n.pcr0], g_cpuConstRegs[_Rt_].UL[0]); xMOV(ptr[&s_iLastPERFCycle[0]], eax); break; case 3: xMOV(eax, ptr[&cpuRegs.cycle]); xMOV(ptr32[&cpuRegs.PERF.n.pcr1], g_cpuConstRegs[_Rt_].UL[0]); xMOV(ptr[&s_iLastPERFCycle[1]], eax); break; } break; case 24: COP0_LOG("MTC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF); break; default: xMOV(ptr32[&cpuRegs.CP0.r[_Rd_]], g_cpuConstRegs[_Rt_].UL[0]); break; } } else { switch (_Rd_) { case 12: iFlushCall(FLUSH_INTERPRETER); _eeMoveGPRtoR(ecx, _Rt_); xFastCall(WriteCP0Status, ecx ); break; case 9: xMOV(ecx, ptr[&cpuRegs.cycle]); _eeMoveGPRtoM((uptr)&cpuRegs.CP0.r[9], _Rt_); xMOV(ptr[&s_iLastCOP0Cycle], ecx); break; case 25: switch(_Imm_ & 0x3F) { case 0: iFlushCall(FLUSH_INTERPRETER); xFastCall(COP0_UpdatePCCR ); _eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pccr, _Rt_); xFastCall(COP0_DiagnosticPCCR ); break; case 1: xMOV(ecx, ptr[&cpuRegs.cycle]); _eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr0, _Rt_); xMOV(ptr[&s_iLastPERFCycle[0]], ecx); break; case 3: xMOV(ecx, ptr[&cpuRegs.cycle]); _eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr1, _Rt_); xMOV(ptr[&s_iLastPERFCycle[1]], ecx); break; } break; case 24: COP0_LOG("MTC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF); break; default: _eeMoveGPRtoM((uptr)&cpuRegs.CP0.r[_Rd_], _Rt_); break; } } }
void recJALR() { int newpc = pc + 4; _allocX86reg(esi, X86TYPE_PCWRITEBACK, 0, MODE_WRITE); _eeMoveGPRtoR(esi, _Rs_); if (EmuConfig.Gamefixes.GoemonTlbHack) { xMOV(ecx, esi); vtlb_DynV2P(); xMOV(esi, eax); } // uncomment when there are NO instructions that need to call interpreter // int mmreg; // if( GPR_IS_CONST1(_Rs_) ) // xMOV(ptr32[&cpuRegs.pc], g_cpuConstRegs[_Rs_].UL[0] ); // else { // int mmreg; // // if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rs_, MODE_READ)) >= 0 ) { // xMOVSS(ptr[&cpuRegs.pc], xRegisterSSE(mmreg)); // } // else if( (mmreg = _checkMMXreg(MMX_GPR+_Rs_, MODE_READ)) >= 0 ) { // xMOVD(ptr[&cpuRegs.pc], xRegisterMMX(mmreg)); // SetMMXstate(); // } // else { // xMOV(eax, ptr[(void*)((int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] )]); // xMOV(ptr[&cpuRegs.pc], eax); // } // } if ( _Rd_ ) { _deleteEEreg(_Rd_, 0); if(EE_CONST_PROP) { GPR_SET_CONST(_Rd_); g_cpuConstRegs[_Rd_].UL[0] = newpc; g_cpuConstRegs[_Rd_].UL[1] = 0; } else { xMOV(ptr32[&cpuRegs.GPR.r[_Rd_].UL[0]], newpc); xMOV(ptr32[&cpuRegs.GPR.r[_Rd_].UL[1]], 0); } } _clearNeededMMXregs(); _clearNeededXMMregs(); recompileNextInstruction(1); if( x86regs[esi.GetId()].inuse ) { pxAssert( x86regs[esi.GetId()].type == X86TYPE_PCWRITEBACK ); xMOV(ptr[&cpuRegs.pc], esi); x86regs[esi.GetId()].inuse = 0; } else { xMOV(eax, ptr[&g_recWriteback]); xMOV(ptr[&cpuRegs.pc], eax); } SetBranchReg(0xffffffff); }