void DWire::begin(uint_fast32_t module) {
this->module = module;
// Initialising the given module as a master
busRole = BUS_ROLE_MASTER;
slaveAddress = 0;
_initMain();
_initMaster(&i2cConfig);
}
void DWire::begin( )
{
// Initialising the given module as a master
busRole = BUS_ROLE_MASTER;
slaveAddress = 0;
_initMain( );
// calculate the number of iterations of a loop to generate
// a delay based on clock speed
// this is needed to handle NACKs in a way that is independent
// of CPU speed and OS (Energia or not)
delayCycles = MAP_CS_getMCLK( ) * 12 / 7905857;
/* Set the EUSCI configuration */
config.selectClockSource = EUSCI_B_I2C_CLOCKSOURCE_SMCLK; // SMCLK Clock Source
config.i2cClk = MAP_CS_getSMCLK( ); // Get the SMCLK clock frequency
config.byteCounterThreshold = 0; // No byte counter threshold
config.autoSTOPGeneration = EUSCI_B_I2C_NO_AUTO_STOP; // No Autostop
if (mode == FAST)
{
config.dataRate = EUSCI_B_I2C_SET_DATA_RATE_400KBPS;
_initMaster( &config );
// accommodate a delay of at least ~30us (~68us measured)
delayCycles = delayCycles * 4;
}
else if(mode == FASTPLUS)
{
config.dataRate = EUSCI_B_I2C_SET_DATA_RATE_1MBPS;
_initMaster( &config );
// accommodate a delay of ~12us (~16us measured)
}
else
{
config.dataRate = EUSCI_B_I2C_SET_DATA_RATE_100KBPS;
_initMaster( &config );
// accommodate a delay of at least ~120us (~130 us measured)
delayCycles = delayCycles * 10;
}
}
