/** Pre initialization - initializing requested modules for basic run of MQX.
*/
int _bsp_pre_init(void) {
KERNEL_DATA_STRUCT_PTR kernel_data;
uint32_t result;
_mqx_int i;
/* Set the CPU type */
_mqx_set_cpu_type(MQX_CPU);
/* Set the bsp exit handler, called by _mqx_exit */
_mqx_set_exit_handler(_bsp_exit_handler);
/* Initialize the MCF548x support functions */
_mcf5441_initialize_support(0);
/*
** Initialize the interrupt handling
*/
_int_set_vector_table(BSP_RAM_INTERRUPT_VECTOR_TABLE);
result = _psp_int_init(BSP_FIRST_INTERRUPT_VECTOR_USED, BSP_LAST_INTERRUPT_VECTOR_USED);
if (result != MQX_OK) {
return result;
} /* Endif */
/* Initialize the timer interrupt */
_time_set_timer_vector(BSP_TIMER_INTERRUPT_VECTOR);
if (_int_install_isr(BSP_TIMER_INTERRUPT_VECTOR, _bsp_timer_isr, NULL) == NULL) {
return MQX_TIMER_ISR_INSTALL_FAIL;
} /* Endif */
#if BSPCFG_HAS_SRAM_POOL
/* When kernel data is placed outside of the SRAM memory create new _BSP_sram_pool in the SRAM,
otherwise if kernel data points to SRAM, the _BSP_sram_pool points to system pool. */
if ( (((uint32_t)__INTERNAL_SRAM_BASE) < (uint32_t)BSP_DEFAULT_START_OF_KERNEL_MEMORY) &&
(((uint32_t)BSP_DEFAULT_START_OF_KERNEL_MEMORY) < ((uint32_t)__INTERNAL_SRAM_BASE + (uint32_t)__INTERNAL_SRAM_SIZE)))
{
_BSP_sram_pool = _mem_get_system_pool_id();
}
else
{
_BSP_sram_pool = _mem_create_pool(__SRAM_POOL, (uint32_t)__INTERNAL_SRAM_BASE + (uint32_t)__INTERNAL_SRAM_SIZE - (uint32_t)__SRAM_POOL);
}
#endif
_GET_KERNEL_DATA(kernel_data);
// Initialize the slice timer to interrupt the specified
// number of times per second
kernel_data->TIMER_HW_REFERENCE = _pit_init_freq(BSP_TIMER, BSP_ALARM_FREQUENCY, BSP_SYSTEM_CLOCK/2, FALSE);
_time_set_hwtick_function(_pit_get_hwticks, (void *)BSP_TIMER);
_time_set_hwticks_per_tick(kernel_data->TIMER_HW_REFERENCE);
_time_set_ticks_per_sec(BSP_ALARM_FREQUENCY);
_pit_unmask_int(BSP_TIMER);
// Initialize and enable the serial UART interrupts
_mcf5441_int_init(BSP_UART0_INT_VECTOR, BSP_UART0_INT_LEVEL, TRUE);
_mcf5441_int_init(BSP_UART2_INT_VECTOR, BSP_UART2_INT_LEVEL, TRUE);
_mcf5441_int_init(BSP_UART4_INT_VECTOR, BSP_UART4_INT_LEVEL, TRUE);
_mcf5441_int_init(BSP_UART6_INT_VECTOR, BSP_UART6_INT_LEVEL, TRUE);
// Install and mask the DMA interrupt handler
/*
_int_install_isr(BSP_ENET_DMA_INTERRUPT, _mcf5445_dma_isr, (void *)0);
_mcf5445_int_init(BSP_ENET_DMA_INTERRUPT, BSP_ENET_DMA_INT_LEVEL, BSP_ENET_DMA_INT_PRIORITY, FALSE);
*/
// Initialize and disable the security engine interrupt
// _mcf54xx_int_init(MCF548x_INT_SEC, BSP_SEC_INT_LEVEL, /*BSP_SEC_INT_PRIORITY, */FALSE);
#if BSP_TRAP_EXCEPTIONS
_int_install_unexpected_isr();
#endif
// Always invalidate the caches even if not enabled. This allows
// us to flush the cache always. If we flush before invalidating
// very bad things happen.
_ICACHE_INVALIDATE();
_DCACHE_INVALIDATE();
if (_mqx_monitor_type == MQX_MONITOR_TYPE_NONE) {
static const PSP_MMU_INIT_STRUCT mmu_init = {
/* We define the default cacheability of non-ACR mapped regions */
/* as non-cacheable and unbuffered */
MCF54XX_CACR_DDCM(MCF54XX_CACHE_NONCACHEABLE_UNBUFFERED)
};
/* Initialize Cache Control Register CACR */
_mmu_init((void *)&mmu_init);
/* Set up 1 instruction and 1 data ACR in two separate SDRAM areas */
/* Caution: Consider memory map in linker command file before changing regions */
/* Note: Second arg to _mmu_add_region is used in mask value in ACR */
result = _mmu_add_region(__CACHED_CODE_START, __CACHED_CODE_END - __CACHED_CODE_START, PSP_MMU_EXEC_ALLOWED);
if (result != MQX_OK) return result;
result = _mmu_add_region(__CACHED_DATA_START, __CACHED_DATA_END - __CACHED_DATA_START, PSP_MMU_WRITE_THROUGH);
if (result != MQX_OK) return result;
/* Copy ACR table into ACR registers */
_MMU_ENABLE();
/* Enable instruction cache and branch history cache in CACR */
_ICACHE_ENABLE(MCF54XX_CACR_IEC | MCF54XX_CACR_BEC);
/* Enable data cache bit in CACR */
_DCACHE_ENABLE(0);
} /* Endif */
#if BSPCFG_ENABLE_CPP
/* initialize C++ constructors */
__cpp_init();
#endif
return 0;
}
uint_32 _bsp_enable_card
(
void
)
{ /* Body */
KERNEL_DATA_STRUCT_PTR kernel_data;
uint_32 result;
_mqx_int i;
/* Set the CPU type */
_mqx_set_cpu_type(MQX_CPU);
/* Set the bsp exit handler, called by _mqx_exit */
_mqx_set_exit_handler(_bsp_exit_handler);
/* Initialize the MCF5301x support functions */
_mcf5301_initialize_support(0);
/*
** Initialize the interrupt handling
*/
_int_set_vector_table(BSP_RAM_INTERRUPT_VECTOR_TABLE);
result = _psp_int_init(BSP_FIRST_INTERRUPT_VECTOR_USED,
BSP_LAST_INTERRUPT_VECTOR_USED);
if (result != MQX_OK) {
return result;
} /* Endif */
/* Initialize the timer interrupt */
_time_set_timer_vector(BSP_TIMER_INTERRUPT_VECTOR);
if (_int_install_isr(BSP_TIMER_INTERRUPT_VECTOR, (void (_CODE_PTR_)(pointer))_bsp_timer_isr, NULL) == NULL) {
return MQX_TIMER_ISR_INSTALL_FAIL;
} /* Endif */
_GET_KERNEL_DATA(kernel_data);
/*
** Initialize the slice timer to interrupt the specified
** number of times per second
*/
kernel_data->TIMER_HW_REFERENCE = _mcf5301_timer_init_freq(BSP_TIMER, BSP_ALARM_FREQUENCY, BSP_SYSTEM_CLOCK, FALSE);
_time_set_hwtick_function(_bsp_get_hwticks, 0);
_time_set_hwticks_per_tick(kernel_data->TIMER_HW_REFERENCE);
_time_set_ticks_per_sec(BSP_ALARM_FREQUENCY);
/* Initialize and enable the timer interrupt */
_mcf5301_int_init(BSP_TIMER_INTERRUPT_VECTOR, BSP_TIMER_INTERRUPT_LEVEL, /*BSP_SLICE_TIMER0_INT_PRIORITY, */TRUE);
/* Initialize and enable the serial UART interrupts */
_mcf5301_int_init(BSP_UART0_INT_VECTOR, BSP_UART0_INT_LEVEL, /*BSP_UART0_INT_PRIORITY, */TRUE);
_mcf5301_int_init(BSP_UART1_INT_VECTOR, BSP_UART1_INT_LEVEL, /*BSP_UART1_INT_PRIORITY, */TRUE);
/* Install and mask the DMA interrupt handler */
/*_int_install_isr(BSP_ENET_DMA_INTERRUPT, _mcf5301_dma_isr, (pointer)0);
_mcf5301_int_init(BSP_ENET_DMA_INTERRUPT, BSP_ENET_DMA_INT_LEVEL, BSP_ENET_DMA_INT_PRIORITY, FALSE);
*/
#if BSP_TRAP_EXCEPTIONS
_int_install_unexpected_isr();
#endif
if (_mqx_monitor_type == MQX_MONITOR_TYPE_NONE) {
static const PSP_MMU_INIT_STRUCT mmu_init = {
/* We define the default cacheability of non-ACR mapped regions */
/* as non-cacheable and unbuffered */
MCF53XX_CACR_DCM(MCF53XX_CACHE_NONCACHEABLE_UNBUFFERED)
};
/* Initialize Cache Control Register CACR */
_mmu_init((pointer)&mmu_init);
/* Set up 1 instruction and 1 data ACR in two separate SDRAM areas */
/* Caution: Consider memory map in linker command file before changing regions */
/* Note: Second arg to _mmu_add_region is used in mask value in ACR */
result = _mmu_add_region(__CACHED_CODE_START, __CACHED_CODE_END - __CACHED_CODE_START, PSP_MMU_EXEC_ALLOWED);
if (result != MQX_OK)
return result;
result = _mmu_add_region(__UNCACHED_DATA_START, __UNCACHED_DATA_END - __UNCACHED_DATA_START, PSP_MMU_DATA_CACHE_INHIBITED);
if (result != MQX_OK)
return result;
/* Copy ACR table into ACR registers */
_MMU_ENABLE();
/* Enable cache
** 0 - Instruction cache only
** 1 - Data cache only
** 2 - Both Instruction & Data cache
*/
_CACHE_ENABLE(2);
} /* Endif */
#if BSPCFG_ENABLE_CPP
/* initialize C++ constructors */
__cpp_init();
#endif
/* Initialize RTC and MQX time */
#if BSPCFG_ENABLE_RTCDEV
_bsp_rtc_io_init ();
_rtc_sync_with_mqx (TRUE);
#endif
#if BSPCFG_ENABLE_IO_SUBSYSTEM
/* Initialize the I/O Sub-system */
result = _io_init();
if (result != MQX_OK) {
return result;
} /* Endif */
#if BSPCFG_ENABLE_TTYA
_mcf53xx_uart_serial_polled_install("ttya:", &_bsp_uart0_init, _bsp_uart0_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_TTYB
_mcf53xx_uart_serial_polled_install("ttyb:", &_bsp_uart1_init, _bsp_uart1_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_TTYC
_mcf53xx_uart_serial_polled_install("ttyc:", &_bsp_uart2_init, _bsp_uart2_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYA
_mcf53xx_uart_serial_int_install("ittya:", &_bsp_uart0_init, _bsp_uart0_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYB
_mcf53xx_uart_serial_int_install("ittyb:", &_bsp_uart1_init, _bsp_uart1_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYC
_mcf53xx_uart_serial_int_install("ittyc:", &_bsp_uart2_init, _bsp_uart2_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_I2C0
_mcf53xx_i2c_polled_install("i2c0:", &_bsp_i2c0_init);
#endif
#if BSPCFG_ENABLE_II2C0
_mcf53xx_i2c_int_install("ii2c0:", &_bsp_i2c0_init);
#endif
#if BSPCFG_ENABLE_SPI0
_mcf5xxx_dspi_polled_install("spi0:", &_bsp_dspi0_init);
#endif
#if BSPCFG_ENABLE_ISPI0
_mcf5xxx_dspi_int_install("ispi0:", &_bsp_dspi0_init);
#endif
#if BSPCFG_ENABLE_EXT_FLASH
result = _io_flashx_install(&_bsp_flashx_init);
#endif
/* Initialize the default serial I/O */
_io_serial_default_init();
#endif /* BSPCFG_ENABLE_IO_SUBSYSTEM */
/*#if !BSP_PEG_PCI_ENABLE
Initialize the PCI in master mode. This will enumerate the bus.
_io_pci_init(TRUE);
#endif
*/
/* Install the GPIO driver */
#if BSPCFG_ENABLE_GPIODEV
_io_gpio_install("gpio:");
#endif
#if BSPCFG_ENABLE_ESDHC
_esdhc_install ("esdhc:", &_bsp_esdhc_init);
#endif
return MQX_OK;
} /* Endbody */
uint_32 _bsp_enable_card
(
void
)
{
KERNEL_DATA_STRUCT_PTR kernel_data;
uint_32 result;
/* Enable Timer */
_e200_enable_timer(BSP_TIMEBASE_USES_EXTERNAL_CLK);
if (_psp_core_num()==0) {
P1_Start( __boot);
}
_GET_KERNEL_DATA(kernel_data);
_mqx_set_cpu_type(MQX_CPU);
/* Set the bsp exit handler, called by _mqx_exit */
_mqx_set_exit_handler(_bsp_exit_handler);
/* Initialize the MPXSxx support functions */
_mpxsxx_initialize_support();
/* Initialize the interrupt handling */
result = _psp_int_init(BSP_FIRST_INTERRUPT_VECTOR_USED, BSP_LAST_INTERRUPT_VECTOR_USED);
if (result != MQX_OK) {
return result;
}
/* Initialize peripheral bridge */
//_qpbridge_init(pbridge_mprot_config, ELEMENTS_OF(pbridge_mprot_config));
/* Initialize Enhanced Interrupt Controller */
result = _qintc_install(_bsp_get_qintc_base_address(), PSP_EXCPT_EXTERNAL);
if (result != MQX_OK) {
return result;
}
/* enable processor recognition of External/Decrementer/Fit interrupts */
_PSP_SET_SR (_PSP_GET_SR() | PSP_MSR_EE);
#if BSPCFG_ENABLE_PIT_TIMER
_qpit_timer_install_kernel(BSPCFG_TIMER_PIT_DEVICE, BSPCFG_TIMER_PIT_CHANNEL,BSP_ALARM_FREQUENCY, BSP_PERI1_CLOCK, BSPCFG_TIMER_INT_LEVEL);
//_e200_decrementer_null_install();
#else
_e200_decrementer_timer_install(BSP_ALARM_FREQUENCY, BSP_TIMEBASE_CLOCK);
#endif
/*------------------------------------------------------------------------*/
/*
** Setup MMU page tables
*/
if (_mqx_monitor_type == MQX_MONITOR_TYPE_NONE) {
_mmu_init(NULL);
// First, mark the three TLBs that the boot code used as 'not-free'
_mmu_reserve_tlb(BSP_FLASH_TLB);
_mmu_reserve_tlb(BSP_RAM_TLB);
_mmu_reserve_tlb(BSP_PERIPHERAL_TLB);
// Next, add regions for RAM.
// Physical Address Virtual Address Size Attributes
_mmu_add_virtual_region(_bsp_vtop(BSP_PRIVATE_RAM_START), BSP_PRIVATE_RAM_START, BSP_PRIVATE_RAM_SIZE, BSP_PRIVATE_RAM_ATTR, BSP_PID_MQX);
_mmu_add_virtual_region(_bsp_vtop(BSP_SHARED_RAM_START), BSP_SHARED_RAM_START, BSP_SHARED_RAM_SIZE, BSP_SHARED_RAM_ATTR, BSP_PID_MQX);
_mmu_add_virtual_region(_bsp_vtopr(BSP_PRIVATE_RAM_START), BSP_REMOTE_PRIVATE_RAM_START,BSP_PRIVATE_RAM_SIZE, BSP_REMOTE_PRIVATE_RAM_ATTR, BSP_PID_MQX);
_mmu_add_virtual_region(_bsp_vtopr(BSP_SHARED_RAM_START), BSP_REMOTE_SHARED_RAM_START, BSP_SHARED_RAM_SIZE, BSP_SHARED_RAM_ATTR, BSP_PID_MQX);
_mmu_add_virtual_region(_bsp_vtop(BSP_UNCACHED_DATA_START),BSP_UNCACHED_DATA_START, BSP_UNCACHED_DATA_SIZE, BSP_UNCACHED_DATA_ATTR, BSP_PID_MQX);
// switch PID from 1 (boot) to 2 (MQX)
_psp_set_pid(BSP_PID_MQX);
// Reclaim the BOOT RAM TLB
_mmu_release_tlb(BSP_RAM_TLB);
#ifndef BSP_CACHE_INHIBIT
_icache_enable(0);
_dcache_enable(0);
#endif
}
#if BSPCFG_ENABLE_CPP
/* initialize C++ constructors */
#if defined(__DCC__) || defined(__HIGHC__)
__init();
#elif defined(__CODEWARRIOR__)
__cpp_init();
#endif
#endif
#if BSPCFG_CORE_MUTEX
result = _core_mutex_install(&_core_mutex_init_info);
if (result != MQX_OK) {
return result;
}
#endif
/*------------------------------------------------------------------------*/
/*
** Initialize the I/O Sub-system
*/
#if BSPCFG_ENABLE_IO_SUBSYSTEM
/* Initialize the I/O Sub-system */
result = _io_init();
if (result != MQX_OK) {
return result;
}
#if PSP_HAS_DEVICE_PROTECTION
if (!_bsp_lwgpio_enable_access(0)) {
return MQX_INVALID_DEVICE;
}
#endif
/* Install device drivers */
#if BSPCFG_ENABLE_TTYA
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_0)) {
_linflexd_serial_polled_install("ttya:", &_bsp_linflexd0_init);
}
#endif
#if BSPCFG_ENABLE_ITTYA
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_0)) {
_linflexd_serial_int_install("ittya:", &_bsp_linflexd0_init);
}
#endif
#if BSPCFG_ENABLE_TTYB
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_1)) {
_linflexd_serial_polled_install("ttyb:", &_bsp_linflexd1_init);
}
#endif
#if BSPCFG_ENABLE_ITTYB
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_1)) {
_linflexd_serial_int_install("ittyb:", &_bsp_linflexd1_init);
}
#endif
#if BSPCFG_ENABLE_TTYC
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_2)) {
_linflexd_serial_polled_install("ttyc:", &_bsp_linflexd2_init);
}
#endif
#if BSPCFG_ENABLE_ITTYC
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_2)) {
_linflexd_serial_int_install("ittyc:", &_bsp_linflexd2_init);
}
#endif
#if BSPCFG_ENABLE_TTYD
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_3)) {
_linflexd_serial_polled_install("ttyd:", &_bsp_linflexd3_init);
}
#endif
#if BSPCFG_ENABLE_ITTYD
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_3)) {
_linflexd_serial_int_install("ittyd:", &_bsp_linflexd3_init);
}
#endif
#if BSPCFG_ENABLE_SPI0
if (_psp_core_peripheral_enabled(CORECFG_SPI_0)) {
_io_spi_install("spi0:", &_bsp_spi0_init);
}
#endif
#if BSPCFG_ENABLE_SPI1
if (_psp_core_peripheral_enabled(CORECFG_SPI_1)) {
_io_spi_install("spi1:", &_bsp_spi1_init);
}
#endif
#if BSPCFG_ENABLE_SPI2
if (_psp_core_peripheral_enabled(CORECFG_SPI_2)) {
_io_spi_install("spi2:", &_bsp_spi2_init);
}
#endif
#if BSPCFG_ENABLE_I2C0
if (_psp_core_peripheral_enabled(CORECFG_I2C_0)) {
_qi2c_polled_install("i2c0:", &_bsp_i2c0_init);
}
#endif
#if BSPCFG_ENABLE_II2C0
if (_psp_core_peripheral_enabled(CORECFG_I2C_0)) {
_qi2c_int_install("ii2c0:", &_bsp_i2c0_init);
}
#endif
#if BSPCFG_ENABLE_I2C1
if (_psp_core_peripheral_enabled(CORECFG_I2C_1)) {
_qi2c_polled_install("i2c1:", &_bsp_i2c1_init);
}
#endif
#if BSPCFG_ENABLE_II2C1
if (_psp_core_peripheral_enabled(CORECFG_I2C_1)) {
_qi2c_int_install("ii2c1:", &_bsp_i2c1_init);
}
#endif
#if BSPCFG_ENABLE_I2C2
if (_psp_core_peripheral_enabled(CORECFG_I2C_2)) {
_qi2c_polled_install("i2c2:", &_bsp_i2c2_init);
}
#endif
#if BSPCFG_ENABLE_II2C2
if (_psp_core_peripheral_enabled(CORECFG_I2C_2)) {
_qi2c_int_install("ii2c2:", &_bsp_i2c2_init);
}
#endif
#if BSPCFG_ENABLE_FLASHX
_io_flashx_install("flashx:", &_bsp_data_flashx_init);
/* code flash support in alpha stage, not tested! */
/* _io_flashx_install("flashx_code:", &_bsp_code_flashx_init); */
#endif
#if BSPCFG_ENABLE_LWADC
#if BSPCFG_ENABLE_LWADC0
if (_psp_core_peripheral_enabled(CORECFG_ADC_0)) {
_lwadc_init(&lwadc0_init);
}
#endif
#if BSPCFG_ENABLE_LWADC1
if (_psp_core_peripheral_enabled(CORECFG_ADC_1)) {
_lwadc_init(&lwadc1_init);
}
#endif
#if BSPCFG_ENABLE_LWADC2
if (_psp_core_peripheral_enabled(CORECFG_ADC_2)) {
_lwadc_init(&lwadc2_init);
}
#endif
#if BSPCFG_ENABLE_LWADC3
if (_psp_core_peripheral_enabled(CORECFG_ADC_3)) {
_lwadc_init(&lwadc3_init);
}
#endif
#endif
#ifdef BSP_DEFAULT_IO_CHANNEL_DEFINED
/* Initialize the default serial I/O */
_io_serial_default_init();
#endif
#endif
return MQX_OK;
}
uint_32 _bsp_enable_card
(
void
)
{
KERNEL_DATA_STRUCT_PTR kernel_data;
uint_32 result;
_GET_KERNEL_DATA(kernel_data);
_mqx_set_cpu_type(PSP_CPU_MPXN20);
/* Set the bsp exit handler, called by _mqx_exit */
_mqx_set_exit_handler(_bsp_exit_handler);
/* Initialize the MPXNxx MMU support functions */
_mpxnxx_initialize_support();
/* === Debugging is not allowed from here === */
/* Initialize the interrupt handling */
result = _psp_int_init(BSP_FIRST_INTERRUPT_VECTOR_USED, BSP_LAST_INTERRUPT_VECTOR_USED);
/* === Debugging may now resume === */
if (result != MQX_OK) {
return result;
}
result = _qintc_install(_bsp_get_qintc_base_address(), PSP_EXCPT_EXTERNAL);
if (result != MQX_OK) {
return result;
}
/* enable processor recognition of External/Decrementer/Fit interrupts */
_PSP_SET_SR (_PSP_GET_SR() | PSP_MSR_EE);
#if 0
/* Install program exception handler */
if (_int_install_isr(PSP_EXCPT_PROGRAM, _psp_program_isr, NULL) == NULL)
{
return _task_get_error();
}
#endif
#if BSPCFG_ENABLE_PIT_TIMER
_qpit_timer_install_kernel(BSPCFG_TIMER_PIT_DEVICE, BSPCFG_TIMER_PIT_CHANNEL, BSP_ALARM_FREQUENCY, BSP_SYSTEM_CLOCK, BSPCFG_TIMER_INT_LEVEL);
#else
_e200_decrementer_timer_install(BSP_ALARM_FREQUENCY, BSP_TIMEBASE_CLOCK);
#endif
/*------------------------------------------------------------------------*/
/*
** Setup MMU page tables
*/
if (_mqx_monitor_type == MQX_MONITOR_TYPE_NONE) {
_mmu_init(NULL);
/* First, mark the three TLBs that the boot code used as 'not-free' */
_mmu_reserve_tlb(BSP_FLASH_TLB);
_mmu_reserve_tlb(BSP_INT_SRAM_TLB);
/* Periph B Modules */
_mmu_reserve_tlb(BSP_PERIPHERAL_TLB);
_mmu_reserve_tlb(BSP_EXT_RAM_TLB);
_mmu_reserve_tlb(BSP_PERIPHERAL_A_TLB);
/* Next, add regions for RAM.
** Physical Address Virtual Address Size Attributes
*/
//_mmu_add_virtual_region((BSP_PRIVATE_RAM_START), BSP_PRIVATE_RAM_START, BSP_PRIVATE_RAM_SIZE, BSP_PRIVATE_RAM_ATTR, BSP_PID_MQX);
//_mmu_add_virtual_region((BSP_UNCACHED_DATA_START),BSP_UNCACHED_DATA_START, BSP_UNCACHED_DATA_SIZE, BSP_UNCACHED_DATA_ATTR, BSP_PID_MQX);
/* switch PID from 1 (boot) to 2 (MQX) */
/*_psp_set_pid(BSP_PID_MQX);*/
/*Reclaim the BOOT RAM TLB*/
/*_mmu_release_tlb(BSP_RAM_TLB);*/
#ifndef BSP_CACHE_INHIBIT
_icache_enable(0);
_dcache_enable(0);
#endif
}
#if BSPCFG_ENABLE_CPP
/* initialize C++ constructors */
#if defined(__DCC__) || defined(__HIGHC__)
__init();
#elif defined(__CODEWARRIOR__)
__cpp_init();
#endif
#endif //BSPCFG_ENABLE_CPP
#if BSPCFG_ENABLE_IO_SUBSYSTEM
/*------------------------------------------------------------------------*/
/*
** Initialize the I/O Sub-system
*/
result = _io_init();
if (result != MQX_OK) {
return result;
} /* Endif */
/* Install device drivers */
#if BSPCFG_ENABLE_TTYA
_lin_serial_polled_install("ttya:", &_bsp_lin0_init);
#endif
#if BSPCFG_ENABLE_ITTYA
_lin_serial_int_install("ittya:", &_bsp_lin0_init);
#endif
#if BSPCFG_ENABLE_TTYB
_lin_serial_polled_install("ttyb:", &_bsp_lin1_init);
#endif
#if BSPCFG_ENABLE_ITTYB
_lin_serial_int_install("ittyb:", &_bsp_lin1_init);
#endif
#if BSPCFG_ENABLE_TTYC
_lin_serial_polled_install("ttyc:", &_bsp_lin2_init);
#endif
#if BSPCFG_ENABLE_ITTYC
_lin_serial_int_install("ittyc:", &_bsp_lin2_init);
#endif
#if BSPCFG_ENABLE_TTYD
_lin_serial_polled_install("ttyd:", &_bsp_lin3_init);
#endif
#if BSPCFG_ENABLE_ITTYD
_lin_serial_int_install("ittyd:", &_bsp_lin3_init);
#endif
#if BSPCFG_ENABLE_TTYE
_lin_serial_polled_install("ttye:", &_bsp_lin4_init);
#endif
#if BSPCFG_ENABLE_ITTYE
_lin_serial_int_install("ittye:", &_bsp_lin4_init);
#endif
#if BSPCFG_ENABLE_TTYF
_lin_serial_polled_install("ttyf:", &_bsp_lin5_init);
#endif
#if BSPCFG_ENABLE_ITTYF
_lin_serial_int_install("ittyf:", &_bsp_lin5_init);
#endif
#if BSPCFG_ENABLE_SPI0
_io_spi_install("spi0:", &_bsp_spi0_init);
#endif
#if BSPCFG_ENABLE_SPI1
_io_spi_install("spi1:", &_bsp_spi1_init);
#endif
#if BSPCFG_ENABLE_SPI2
_io_spi_install("spi2:", &_bsp_spi2_init);
#endif
#if BSPCFG_ENABLE_SPI3
_io_spi_install("spi3:", &_bsp_spi3_init);
#endif
#if BSPCFG_ENABLE_FLASHX
_io_flashx_install("flashx:", &_bsp_flashx_init);
#endif
#if BSPCFG_ENABLE_I2C0
_qi2c_polled_install("i2c0:", &_bsp_i2c0_init);
#endif
#if BSPCFG_ENABLE_II2C0
_qi2c_int_install("ii2c0:", &_bsp_i2c0_init);
#endif
#if BSPCFG_ENABLE_I2C1
_qi2c_polled_install("i2c1:", &_bsp_i2c1_init);
#endif
#if BSPCFG_ENABLE_II2C1
_qi2c_int_install("ii2c1:", &_bsp_i2c1_init);
#endif
#if BSPCFG_ENABLE_I2C2
_qi2c_polled_install("i2c2:", &_bsp_i2c2_init);
#endif
#if BSPCFG_ENABLE_II2C2
_qi2c_int_install("ii2c2:", &_bsp_i2c2_init);
#endif
#if BSPCFG_ENABLE_I2C3
_qi2c_polled_install("i2c3:", &_bsp_i2c3_init);
#endif
#if BSPCFG_ENABLE_II2C3
_qi2c_int_install("ii2c3:", &_bsp_i2c3_init);
#endif
#if BSPCFG_ENABLE_RTCDEV
_rtc_init (RTC_INIT_FLAG_CLEAR | RTC_INIT_FLAG_RESET | RTC_INIT_FLAG_ENABLE);
#endif
#if BSPCFG_ENABLE_LWADC
#if BSPCFG_ENABLE_LWADC0
_lwadc_init(&lwadc0_init);
#endif
#endif
/* Initialize the default serial I/O */
_io_serial_default_init();
#endif // BSPCFG_ENABLE_IO_SUBSYSTEM
return MQX_OK;
}