/* Checks "l2cr=xxxx" command-line option */ int __init ppc_setup_l2cr(char *str) { if (cpu_has_feature(CPU_FTR_L2CR)) { unsigned long val = simple_strtoul(str, NULL, 0); printk(KERN_INFO "l2cr set to %lx\n", val); _set_L2CR(0); /* force invalidate by disable cache */ _set_L2CR(val); /* and enable it */ } return 1; }
int __init ppc_setup_l2cr(char *str) { if (cpu_has_feature(CPU_FTR_L2CR)) { unsigned long val = simple_strtoul(str, NULL, 0); printk(KERN_INFO "l2cr set to %lx\n", val); _set_L2CR(0); _set_L2CR(val); } return 1; }
/* * Called very early, device-tree isn't unflattened */ static int __init c2k_probe(void) { unsigned long root = of_get_flat_dt_root(); if (!of_flat_dt_is_compatible(root, "GEFanuc,C2K")) return 0; printk(KERN_INFO "Detected a GEFanuc C2K board\n"); _set_L2CR(0); _set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2I); return 1; }
static void __init sandpoint_setup_arch(void) { loops_per_jiffy = 100000000 / HZ; #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = to_kdev_t(0x00FF); /* /dev/nfs pseudo device */ #else ROOT_DEV = to_kdev_t(0x0301); /* /dev/hda1 IDE disk */ #endif /* Lookup PCI host bridges */ sandpoint_find_bridges(); #ifdef CONFIG_SERIAL sandpoint_early_serial_map(); #endif #ifdef CONFIG_DUMMY_CONSOLE conswitchp = &dummy_con; #endif printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n"); /* DINK32 12.3 and below do not correctly enable any caches. * We will do this now with good known values. Future versions * of DINK32 are supposed to get this correct. */ if (cur_cpu_spec[0]->cpu_features & CPU_FTR_SPEC7450) /* 745x is different. We only want to pass along enable. */ _set_L2CR(L2CR_L2E); else if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR) /* All modules have 1MB of L2. We also assume that an * L2 divisor of 3 will work. */ _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF); #if 0 /* Untested right now. */ if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR) { /* Magic value. */ _set_L3CR(0x8f032000); } #endif }
static void __init taiga_setup_arch(void) { loops_per_jiffy = 50000000 / HZ; #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif if (ppc_md.progress) ppc_md.progress("taiga_setup_arch: setup_bridge", 0); /* setup PCI host bridge */ taiga_setup_bridge(); #ifdef CONFIG_DUMMY_CONSOLE conswitchp = &dummy_con; #endif printk(KERN_INFO "Taiga Platform\n"); printk(KERN_INFO "Jointly ported by Freescale and Tundra Semiconductor\n"); printk(KERN_INFO "Enabling L2 cache then enabling the HID0 prefetch engine.\n"); _set_L2CR(L2CR_L2E); taiga_l2cr_prefetch_enable(); TODC_INIT(TODC_TYPE_MK48T35, 0, 0, TAIGA_NVRAM_BASE_ADDR, 8); }
static void __init pcore_setup_arch(void) { /* init to some ~sane value until calibrate_delay() runs */ loops_per_jiffy = 50000000/HZ; /* Lookup PCI host bridges */ board_type = pcore_find_bridges(); #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_SDA2; #endif printk(KERN_INFO "Force PowerCore "); if (board_type == PCORE_TYPE_6750) printk("6750\n"); else printk("680\n"); printk(KERN_INFO "Port by MontaVista Software, Inc. ([email protected])\n"); _set_L2CR(L2CR_L2E | _get_L2CR()); }
static void __init katana_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("katana_setup_arch: enter", 0); set_tb(0, 0); #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_SDA2; #endif /* * Set up the L2CR register. * * 750FX has only L2E, L2PE (bits 2-8 are reserved) * DD2.0 has bug that requires the L2 to be in WRT mode * avoid dirty data in cache */ if (PVR_REV(mfspr(SPRN_PVR)) == 0x0200) { printk(KERN_INFO "DD2.0 detected. Setting L2 cache" "to Writethrough mode\n"); _set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT); } else _set_L2CR(L2CR_L2E | L2CR_L2PE); if (ppc_md.progress) ppc_md.progress("katana_setup_arch: calling setup_bridge", 0); katana_setup_bridge(); katana_setup_peripherals(); katana_enable_ipmi(); katana_bus_frequency = katana_bus_freq(cpld_base); printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n"); if (ppc_md.progress) ppc_md.progress("katana_setup_arch: exit", 0); }
void __init core99_init_l2(void) { int cpu = smp_processor_id(); if (!(cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR)) return; if (cpu == 0){ core99_l2_cache = _get_L2CR(); printk("CPU0: L2CR is %lx\n", core99_l2_cache); } else { printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR()); _set_L2CR(0); _set_L2CR(core99_l2_cache); printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache); } }
/************************************************************************** * FUNCTION: chestnut_setup_arch * * DESCRIPTION: ppc_md machine configuration callback * ****/ static void __init chestnut_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("chestnut_setup_arch: enter", 0); /* init to some ~sane value until calibrate_delay() runs */ loops_per_jiffy = 50000000 / HZ; /* if the time base value is greater than bus freq/4 (the TB and * decrementer tick rate) + signed integer rollover value, we * can spend a fair amount of time waiting for the rollover to * happen. To get around this, initialize the time base register * to a "safe" value. */ set_tb(0, 0); #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_SDA2; #endif /* * Set up the L2CR register. */ _set_L2CR(_get_L2CR() | L2CR_L2E); chestnut_setup_bridge(); chestnut_setup_peripherals(); #ifdef CONFIG_DUMMY_CONSOLE conswitchp = &dummy_con; #endif #if defined(CONFIG_SERIAL_8250) chestnut_early_serial_map(); #endif /* Identify the system */ printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n"); printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc." " ([email protected])\n"); if (ppc_md.progress) ppc_md.progress("chestnut_setup_arch: exit", 0); }
/* * Called very early, device-tree isn't unflattened */ static int __init prpmc2800_probe(void) { unsigned long root = of_get_flat_dt_root(); unsigned long len = PLATFORM_NAME_MAX; void *m; if (!of_flat_dt_is_compatible(root, "motorola,PrPMC2800")) return 0; /* Update ppc_md.name with name from dt */ m = of_get_flat_dt_prop(root, "model", &len); if (m) strncpy(prpmc2800_platform_name, m, min((int)len, PLATFORM_NAME_MAX - 1)); _set_L2CR(_get_L2CR() | L2CR_L2E); return 1; }
static void __init ev64360_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("ev64360_setup_arch: enter", 0); set_tb(0, 0); #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_SDA2; #endif /* * Set up the L2CR register. */ _set_L2CR(L2CR_L2E | L2CR_L2PE); if (ppc_md.progress) ppc_md.progress("ev64360_setup_arch: calling setup_bridge", 0); ev64360_setup_bridge(); ev64360_setup_peripherals(); ev64360_bus_frequency = ev64360_bus_freq(); printk(KERN_INFO "%s %s port (C) 2005 Lee Nicks " "([email protected])\n", BOARD_VENDOR, BOARD_MACHINE); if (ppc_md.progress) ppc_md.progress("ev64360_setup_arch: exit", 0); }
static void __init sandpoint_setup_arch(void) { /* Probe for Sandpoint model */ sandpoint_probe_type(); if (sandpoint_is_x2) epic_serial_mode = 0; loops_per_jiffy = 100000000 / HZ; #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif /* Lookup PCI host bridges */ sandpoint_find_bridges(); if (strncmp (cur_ppc_sys_spec->ppc_sys_name, "8245", 4) == 0) { bd_t *bp = (bd_t *)__res; struct plat_serial8250_port *pdata; pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0); if (pdata) { pdata[0].uartclk = bp->bi_busfreq; } #ifdef CONFIG_SANDPOINT_ENABLE_UART1 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1); if (pdata) { pdata[0].uartclk = bp->bi_busfreq; } #else ppc_sys_device_remove(MPC10X_UART1); #endif } printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n"); printk(KERN_INFO "Port by MontaVista Software, Inc. ([email protected])\n"); /* DINK32 12.3 and below do not correctly enable any caches. * We will do this now with good known values. Future versions * of DINK32 are supposed to get this correct. */ if (cpu_has_feature(CPU_FTR_SPEC7450)) /* 745x is different. We only want to pass along enable. */ _set_L2CR(L2CR_L2E); else if (cpu_has_feature(CPU_FTR_L2CR)) /* All modules have 1MB of L2. We also assume that an * L2 divisor of 3 will work. */ _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF); #if 0 /* Untested right now. */ if (cpu_has_feature(CPU_FTR_L3CR)) { /* Magic value. */ _set_L3CR(0x8f032000); } #endif }