int util_get_plus_args_str() {
/* Example use:
invocation script (bosox is passed in as first argument)
-----------------
set basename = $1
verilog mymodule.v +tst_file_name${basename}.tst +log_file_name${basename}.log
+err_file_name${basename}.err +result_file_name${basename}.result
mymodule.v
----------
reg [32*8:1] tst_file_name; // plus argument string value
reg [32*8:1] err_file_name; // plus argument string value
reg [32*8:1] log_file_name; // plus argument string value
reg [32*8:1] result_file_name; // plus argument string value
integer plus_arg_ok; // 0 if ok, 1 if no plus argument value
initial
begin
// get strings from plus argument values
plus_arg_ok = $util_get_plus_args_str("tst_file_name", tst_file_name);
plus_arg_ok = $util_get_plus_args_str("err_file_name", err_file_name);
plus_arg_ok = $util_get_plus_args_str("log_file_name", log_file_name);
plus_arg_ok = $util_get_plus_args_str("result_file_name",result_file_name);
$display("tst_file_name is %s", tst_file_name);
$display("err_file_name is %s", err_file_name);
$display("log_file_name is %s", log_file_name);
$display("result_file_name is %s", result_file_name);
end
*/
/* Input is string
Returning value is string.
*/
handle wrk_out;
char *strArgIn;
int sizeOut,sizeS_in;
int numArgs;
int cnt,size;
char *buffer, *bufferout;
s_setval_value value_out;
s_setval_delay delay_out;
delay_out.model = accNoDelay;
delay_out.time.type = accRealTime;
delay_out.time.real = 0.0;
value_out.format = accHexStrVal;
acc_initialize();
numArgs = tf_nump();
if(numArgs !=2) {
tf_error("$get_plus_arg_string must have two arguments");
tf_putp(0,VERILOG_ERROR);
return(VERILOG_ERROR);
}
/* Fetch the input register and size */
wrk_out = acc_handle_tfarg(2);
sizeOut = (acc_fetch_size(wrk_out)/8);
/* Get the string value */
strArgIn = mc_scan_plusargs(tf_getcstringp(1));
if (strArgIn == NULL) {
if (DEBUG_PLUS_ARGS)
io_printf("get_plus_args_str(): Matching string is not found: %s.\n", tf_getcstringp(1));
tf_putp(0,VERILOG_ERROR);
return(VERILOG_ERROR);
}
if (strArgIn) {
if (DEBUG_PLUS_ARGS)
io_printf("get_plus_args_str(): Got string value: %s\n",strArgIn);
}
else {
io_printf("get_plus_args_str(): Bad input string value.\n");
tf_putp(0,VERILOG_ERROR);
return(VERILOG_ERROR);
}
/* Build new string */
sizeS_in = strlen(strArgIn);
bufferout = (char *) malloc(sizeS_in + 1);
sprintf(bufferout, "%s",strArgIn);
if (sizeOut < sizeS_in) {
tf_error("get_plus_args_str(): Register %s is not large enough.\n",
acc_fetch_fullname(wrk_out));
tf_putp(0,VERILOG_ERROR);
return(VERILOG_ERROR);
}
size = sizeS_in*2;
buffer = (char *) malloc(size + 1);
for (cnt =0; cnt < size; cnt +=2){
if (cnt < size){
/* Convert string into HEX code */
sprintf(&buffer[cnt],"%x",bufferout[cnt/2]);
}
}
/* Null out the rest of the register
else {
buffer[cnt] = '\0';
buffer[cnt +1] = '\0';
}
*/
/* assign buffer to the verilog register */
value_out.value.str = buffer;
acc_set_value(wrk_out, &value_out, &delay_out);
tf_putp(0,VERILOG_OK);
acc_close();
free(buffer);
free(bufferout);
return(VERILOG_OK);
}
/*
* process one instance and recursively process all under instances
* processing is top down depth first
*/
static int process_inst(handle upinst)
{
handle scope, inst, net, bit, var, prim, term, port;
static int varlist[] = { accReg, accIntegerVar, accTimeVar, 0 };
io_printf("... setting up vcls for instance %s\n",
acc_fetch_fullname(upinst));
/* first strength vcls on all nets */
/* first add vcls for nets */
io_printf("... vcls for wires\n");
for (net = acc_next_net(upinst, NULL); net != NULL;
net = acc_next_net(upinst, net))
{
if (acc_fetch_size(net) == 1) add_vcl(net);
else
{
/* for vector wires, must put vcl on bit - need to access strength */
for (bit = acc_next_bit(net, NULL); bit != NULL;
bit = acc_next_bit(net, bit)) add_vcl(bit);
}
}
/* then variables */
io_printf("... vcls for variables\n");
for (var = acc_next(varlist, upinst, NULL); var != NULL;
var = acc_next(varlist, upinst, var)) add_vcl(var);
io_printf("... vcls for primitive terminals\n");
/* then primitives output terminals */
for (prim = acc_next_primitive(upinst, NULL); prim != NULL;
prim = acc_next_primitive(upinst, prim))
{
for (term = acc_next_terminal(prim, NULL); term != NULL;
term = acc_next_terminal(prim, term))
{
/* only output terminals can have vcl added */
if (acc_fetch_direction(term) == accInput) continue;
add_vcl(term);
}
}
/* then module ports */
io_printf("... vcls for ports\n");
for (port = acc_next_port(upinst, NULL); port != NULL;
port = acc_next_port(upinst, port))
{
if (acc_fetch_size(port) == 1) add_vcl(port);
else
{
/* for vector ports, must put vcl on bit - need to access strength */
for (bit = acc_next_bit(port, NULL); bit != NULL;
bit = acc_next_bit(port, bit)) add_vcl(bit);
}
}
/* finally all variables in contained scopes */
for (scope = acc_next_scope(upinst, NULL); scope != NULL;
scope = acc_next_scope(upinst, scope))
{
/* final step setup vcls for contained scopes */
setup_1scope_chgcbs(scope);
}
for (inst = NULL;;)
{
if ((inst = acc_next_child(upinst, inst)) == NULL) break;
process_inst(inst);
}
return(0);
}
