unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ current = acpi_create_madt_lapics(current); /* IOAPIC */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); /* LAPIC_NMI */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) current, 0, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE, 0x01); current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) current, 1, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE, 0x01); /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); return current; }
unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 2); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 3); /* Write SB900 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb900, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0xF); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edge-triggered, Active high */ /* create all subtables for processors */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 2, 5, 1); current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 3, 5, 1); /* 1: LINT1 connect to NMI */ return current; }
unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); /* TODO: Remove the hardcode */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, 0xFEC20000, 24); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0xF); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edige-triggered, Active high */ /* create all subtables for processors */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); /* 1: LINT1 connect to NMI */ return current; }
unsigned long acpi_fill_madt(unsigned long current) { device_t dev; u32 dword; u32 gsi_base=0; uint32_t apicid_sp5100; uint32_t apicid_sr5650; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); apicid_sp5100 = 0x20; apicid_sr5650 = apicid_sp5100 + 1; /* Write SB700 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sp5100, IO_APIC_ADDR, gsi_base); /* IOAPIC on rs5690 */ gsi_base += 24; /* SB700 has 24 IOAPIC entries. */ dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (dev) { pci_write_config32(dev, 0xF8, 0x1); dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sr5650, dword, gsi_base); } /* bus, source, gsirq, flags */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0xF); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edge-triggered, Active high */ /* create all subtables for processors */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); /* 1: LINT1 connect to NMI */ return current; }
unsigned long acpi_fill_madt(unsigned long current) { /* Local Apic */ current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 0, 0); /* IOAPIC */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000f); // low/level /* LAPIC_NMI */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) current, 0, 0x0005, 1); // high/edge return current; }
unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint) { device_t cpu; int cpu_index = 0; for(cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { continue; } if (!cpu->enabled) { continue; } current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint); cpu_index++; } return current; }
unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *) current, 2, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((struct acpi_madt_irqoverride *) current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((struct acpi_madt_irqoverride *) current, 0, 9, 9, 0xD); current += acpi_create_madt_irqoverride((struct acpi_madt_irqoverride *) current, 0, 0xB, 0xB, 0xD); acpi_create_madt_lapic_nmi((struct acpi_madt_lapic_nmi *)current, 0, 0, 0); return current; /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edge-triggered, Active high */ }
unsigned long acpi_fill_madt(unsigned long current) { device_t dev; u32 dword; u32 gsi_base = 0; u32 apicid_sp5100; u32 apicid_sr5650; /* * AGESA v5 Apply apic enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * For systems with < 16 APICs, put the Local-APICs at 0..n and * put the IO-APICs at (n + 1)..z */ if (CONFIG_MAX_CPUS >= 16) apicid_sp5100 = 0x0; else apicid_sp5100 = CONFIG_MAX_CPUS + 1; apicid_sr5650 = apicid_sp5100 + 1; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write sp5100 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sp5100, IO_APIC_ADDR, 0 ); /* IOAPIC on rs5690 */ gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */ dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (dev) { pci_write_config32(dev, 0xF8, 0x1); dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sr5650, dword, gsi_base ); } current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, //BUS 0, //SOURCE 2, //gsirq 0 //flags ); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edge-triggered, Active high */ /* create all subtables for processors */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); /* 1: LINT1 connect to NMI */ return current; }