static unsigned long acpi_fill_dmar(unsigned long current)
{
int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL);
int stepping = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_CLASS_REVISION);
unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1);
current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x1b, 0);
acpi_dmar_drhd_fixup(tmp, current);
if (stepping != STEPPING_B2) {
tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE2);
current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x2, 0);
current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x2, 1);
acpi_dmar_drhd_fixup(tmp, current);
}
if (me_active) {
tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE3);
current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x3, 0);
current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x3, 1);
current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x3, 2);
current += acpi_create_dmar_drhd_ds_pci(current, 0, 0x3, 3);
acpi_dmar_drhd_fixup(tmp, current);
}
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE4);
/* TODO: reserve GTT for 0.2.0 and 0.2.1? */
return current;
}
static unsigned long acpi_fill_dmar(unsigned long current)
{
const struct device *const igfx = dev_find_slot(0, PCI_DEVFN(2, 0));
if (igfx && igfx->enabled) {
const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1);
current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0);
current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 1);
acpi_dmar_drhd_fixup(tmp, current);
}
const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current,
DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE2);
current += acpi_create_dmar_drhd_ds_ioapic(current,
2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
size_t i;
for (i = 0; i < 8; ++i)
current += acpi_create_dmar_drhd_ds_msi_hpet(current,
0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, i);
acpi_dmar_drhd_fixup(tmp, current);
return current;
}
