/***************************************************************************//** * @brief Initializes the AD9467 FPGA core. * * @param dco_delay - ADC delay. * * @return None. *******************************************************************************/ void adc_setup(u32 dco_delay) { Xil_Out32((CF_BASEADDR + CF_REG_PN_TYPE), CF_PN_TYPE_BIT(0)); // Select PN9 Xil_Out32((CF_BASEADDR + CF_REG_DATA_SELECT), CF_DATA_SELECT_BIT(0)); // First byte from DDR appears on rising edge Xil_Out32((CF_BASEADDR + CF_REG_DELAY_CTRL), 0x00000); // clear bits Xil_Out32((CF_BASEADDR + CF_REG_DELAY_CTRL), CF_DELAY_CTRL_SEL(1) | CF_DELAY_CTRL_WR_ADDR(0xF) | // delay write CF_DELAY_CTRL_WR_DATA(0x1F)); Xil_Out32((CF_BASEADDR + CF_REG_DELAY_CTRL), CF_DELAY_CTRL_SEL(1) | // delay write CF_DELAY_CTRL_WR_ADDR(0xF) | CF_DELAY_CTRL_WR_DATA(0x1F)); ad9467_test_mode(5); // Select PN 23 sequence test mode ad9467_output_format(0); // Select output format as offset binary ad9467_transfer(); // Synchronously update registers Xil_Out32((CF_BASEADDR + CF_REG_PN_TYPE), CF_PN_TYPE_BIT(1)); ad9467_dco_clock_invert(0); // Activates the non-inverted DCO clock ad9467_transfer(); // Synchronously update registers xil_printf("AD9467[REG_OUT_PHASE]: %02x\n\r", ad9467_dco_clock_invert(-1)); // reads the dco clock invert bit state delay_ms(10); if (adc_delay()) { ad9467_dco_clock_invert(1); // Activates the inverted DCO clock ad9467_transfer(); // Synchronously update registers xil_printf("AD9467[REG_OUT_PHASE]: %02x\n\r", ad9467_dco_clock_invert(-1)); // reads the dco clock invert bit state delay_ms(10); if (adc_delay()) { xil_printf("adc_setup: can not set a zero error delay!\n\r"); adc_delay_1(0); } } }
/***************************************************************************//** * @brief Configures the AD9467 device to run in the selected test mode * and checks if the read data pattern corresponds to the expected * values for the set test mode. * * @param mode - The test mode. Range 0 ..7 * 0 - test mode off * 1 - midscale short * 2 - +FS short * 3 - -FS short * 4 - checkerboard output * 5 - PN 23 sequence * 6 - PN 9 sequence * 7 - one/zero word toggle * @param format - Sets the data format: * 0 - offset binary * 1 - twos complement * 2 - gray code * * @return None. *******************************************************************************/ void adc_test(u32 mode, u32 format) { u32 n; u32 rdata; u32 edata; edata = 0; ad9467_output_format(format); ad9467_test_mode(mode); ad9467_transfer(); adc_capture(16, DDR_BASEADDR); xil_printf("adc_test(): mode(%2d), format(%2d)\n\r", mode, format); if ((mode == 0x5) || (mode == 0x6)) { if (format == 0x1) return; Xil_Out32((CF_BASEADDR + CF_REG_PN_TYPE), ((mode == 0x5) ? 0x01 : 0x00)); delay_ms(10); Xil_Out32((CF_BASEADDR + CF_REG_DATA_MONITOR), CF_DATA_MONITOR_PN_ERR | CF_DATA_MONITOR_PN_SYNC | CF_DATA_MONITOR_PN_OVER_RNG); // write ones to clear bits delay_ms(100); if ((Xil_In32(CF_BASEADDR + CF_REG_DATA_MONITOR) & (CF_DATA_MONITOR_PN_ERR | CF_DATA_MONITOR_PN_SYNC | CF_DATA_MONITOR_PN_OVER_RNG)) != 0) { xil_printf(" ERROR: PN status(%04x).\n\r", Xil_In32(CF_BASEADDR + CF_REG_DATA_MONITOR)); } return; } for (n = 0; n < 32; n++) { rdata = Xil_In32(DDR_BASEADDR+(n*4)); if ((mode == 0x1) && (format == 0)) edata = 0x80008000; if ((mode == 0x2) && (format == 0)) edata = 0xffffffff; if ((mode == 0x3) && (format == 0)) edata = 0x00000000; if ((mode == 0x1) && (format == 1)) edata = 0x00000000; if ((mode == 0x2) && (format == 1)) edata = 0x7fff7fff; if ((mode == 0x3) && (format == 1)) edata = 0x80008000; if (((mode == 0x4) || (mode == 0x7)) && (n == 0)) { edata = (rdata & 0xffff); } if ((mode == 0x4) && (n == 0)) edata = (edata == 0xaaaa) ? 0x5555aaaa : 0xaaaa5555; if ((mode == 0x7) && (n == 0)) edata = (edata == 0xffff) ? 0x0000ffff : 0xffff0000; if (rdata != edata) { xil_printf(" ERROR[%2d]: rcv(%08x), exp(%08x)\n\r", n, rdata, edata); } } }
/***************************************************************************//** * @brief Main function. * * @return 0. *******************************************************************************/ int main(){ uint32_t mode; Xil_ICacheEnable(); Xil_DCacheEnable(); /* AD9467 Setup. */ ad9467_setup(SPI_DEVICE_ID, 0); /* AD9517 Setup. */ ad9517_setup(SPI_DEVICE_ID, 1); // Initialize device. ad9517_power_mode(3, 0); // Set channel 3 for normal operation ad9517_frequency(3, 250000000); // Set the channel 3 frequency to 250Mhz ad9517_update(); // Update registers /* Read the device ID for AD9467 and AD9517. */ xil_printf("\n\r********************************************************************\r\n"); xil_printf(" ADI AD9467-FMC-EBZ Reference Design\n\r"); xil_printf(" AD9467 CHIP ID: 0x%02x\n\r", ad9467_read(AD9467_REG_CHIP_ID)); xil_printf(" AD9467 CHIP GRADE: 0x%02x\n\r", ad9467_read(AD9467_REG_CHIP_GRADE)); xil_printf(" AD9517 CHIP ID: 0x%02x", ad9517_read(AD9517_REG_PART_ID)); xil_printf("\n\r********************************************************************\r\n"); /* AD9467 test. */ adc_setup(0); for (mode = MIDSCALE; mode <= ONE_ZERO_TOGGLE; mode++) // Data pattern checks { adc_test(mode, OFFSET_BINARY); // Data format is offset binary adc_test(mode, TWOS_COMPLEMENT); // Data format is twos complement } xil_printf("Testing done.\n\r"); /* AD9467 Setup for data acquisition */ ad9467_output_invert(0); // Output invert Off ad9467_transfer(); // Synchronously update registers ad9467_output_format(0); // Offset binary ad9467_transfer(); // Synchronously update registers ad9467_reset_PN9(0); // Clear PN9 bit ad9467_transfer(); // Synchronously update registers ad9467_reset_PN23(0); // Clear PN23 bit ad9467_transfer(); // Synchronously update registers ad9467_test_mode(0); // Test mode Off ad9467_transfer(); // Synchronously update registers xil_printf("Start capturing data...\n\r"); while(1) { adc_capture(1024, DDR_BASEADDR); } Xil_DCacheDisable(); Xil_ICacheDisable(); return 0; }
/***************************************************************************//** * @brief Main function. * * @return 0. *******************************************************************************/ int main(){ u32 mode; Xil_ICacheEnable(); Xil_DCacheEnable(); /* AD9467 Setup. */ ad9467_setup(XPAR_AXI_SPI_0_BASEADDR, 1); /* AD9517 Setup. */ ad9517_setup(XPAR_AXI_SPI_0_BASEADDR, 2); // Initialize device. ad9517_power_mode(3, 0); // Set channel 3 for normal operation ad9517_frequency(3, 250000000); // Set the channel 3 frequency to 250Mhz ad9517_update(); // Update registers /* Read the device ID for AD9467 and AD9517. */ xil_printf("AD9467[REG_CHIP_ID]: %02x\n\r", ad9467_read(AD9467_REG_CHIP_ID)); xil_printf("AD9467[REG_CHIP_GRADE]: %02x\n\r", ad9467_read(AD9467_REG_CHIP_GRADE)); xil_printf("AD9517[REG_PART_ID]: %02x\n\r", ad9517_read(AD9517_REG_PART_ID)); /* AD9467 test. */ adc_setup(0); for (mode = 0x01; mode <= 0x07; mode++) // Data pattern checks { adc_test(mode, 0x0); // Data format is offset binary adc_test(mode, 0x1); // Data format is twos complement } ad9467_output_invert(0); // Output invert Off ad9467_output_format(0); // Offset binary ad9467_reset_PN9(0); // Clear PN9 bit ad9467_reset_PN23(0); // Clear PN23 bit ad9467_test_mode(0); // Test mode Off ad9467_transfer(); // Synchronously update registers xil_printf("done\n\r"); Xil_DCacheDisable(); Xil_ICacheDisable(); return 0; }
/***************************************************************************//** * @brief Configures the AD9467 device to run in the selected test mode * and checks if the read data pattern corresponds to the expected * values for the set test mode. * * @param mode - The test mode. Range 0 ..7 * 0 - test mode off * 1 - midscale short * 2 - +FS short * 3 - -FS short * 4 - checkerboard output * 5 - PN 23 sequence * 6 - PN 9 sequence * 7 - one/zero word toggle * @param format - Sets the data format: * 0 - offset binary * 1 - twos complement * 2 - gray code * * @return None. *******************************************************************************/ void adc_test(uint32_t mode, uint32_t format) { uint32_t n; uint32_t rdata; uint32_t edata = 0; uint32_t error = 0; ad9467_output_format(format); ad9467_test_mode(mode); ad9467_transfer(); adc_capture(64, DDR_BASEADDR); DisplayTestMode(mode, format); if ((mode == PN_23_SEQUENCE) || (mode == PN_9_SEQUENCE)) { if (format == TWOS_COMPLEMENT) { xil_printf(" Test skipped\r\n"); return; } adc_set_pnsel(0, ((mode == PN_23_SEQUENCE) ? ADC_PN23A : ADC_PN9)); delay_ms(10); Xil_Out32((CF_BASEADDR + CF_REG_DATA_MONITOR), CF_DATA_MONITOR_PN_ERR | CF_DATA_MONITOR_PN_SYNC | CF_DATA_MONITOR_PN_OVER_RNG); // write ones to clear bits delay_ms(100); if ((Xil_In32(CF_BASEADDR + CF_REG_DATA_MONITOR) & (CF_DATA_MONITOR_PN_ERR | CF_DATA_MONITOR_PN_SYNC | CF_DATA_MONITOR_PN_OVER_RNG)) != 0) { xil_printf(" ERROR: PN status(%04x).\n\r", Xil_In32(CF_BASEADDR + CF_REG_DATA_MONITOR)); } else { xil_printf(" Test passed\r\n"); } return; } for (n = 0; n < 32; n++) { rdata = Xil_In32(DDR_BASEADDR+(n*4)); if ((mode == MIDSCALE) && (format == OFFSET_BINARY)) edata = 0x80008000; if ((mode == POS_FULLSCALE) && (format == OFFSET_BINARY)) edata = 0xffffffff; if ((mode == NEG_FULLSCALE) && (format == OFFSET_BINARY)) edata = 0x00000000; if ((mode == MIDSCALE) && (format == TWOS_COMPLEMENT)) edata = 0x00000000; if ((mode == POS_FULLSCALE) && (format == TWOS_COMPLEMENT)) edata = 0x7fff7fff; if ((mode == NEG_FULLSCALE) && (format == TWOS_COMPLEMENT)) edata = 0x80008000; if (((mode == CHECKERBOARD) || (mode == ONE_ZERO_TOGGLE)) && (n == 0)) { edata = (rdata & 0xffff); } if ((mode == CHECKERBOARD) && (n == 0)) edata = (edata == 0xaaaa) ? 0x5555aaaa : 0xaaaa5555; if ((mode == ONE_ZERO_TOGGLE) && (n == 0)) edata = (edata == 0xffff) ? 0x0000ffff : 0xffff0000; if (rdata != edata) { xil_printf(" ERROR[%2d]: rcv(%08x), exp(%08x)\n\r", n, rdata, edata); error = 1; } } if(error == 0) { xil_printf(" Test passed\r\n"); } }