/**
* @brief Low level ADC driver initialization.
*
* @notapi
*/
void adc_lld_init(void) {
ADC->CCR = STM32_ADC_ADCPRE;
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
#endif
#if STM32_ADC_USE_ADC2
/* Driver initialization.*/
adcObjectInit(&ADCD2);
ADCD2.adc = ADC2;
ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
#endif
#if STM32_ADC_USE_ADC3
/* Driver initialization.*/
adcObjectInit(&ADCD3);
ADCD3.adc = ADC3;
ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
STM32_DMA_CR_EN;
#endif
/* The shared vector is initialized on driver initialization and never
disabled.*/
nvicEnableVector(ADC_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
}
/**
* @brief Low level ADC driver initialization.
*
* @notapi
*/
void adc_lld_init(void) {
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
ADCD1.dmastp = STM32_DMA1_STREAM1;
ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_TEIE;
/* Temporary activation.*/
rccEnableADC1(FALSE);
ADC1->CR1 = 0;
ADC1->CR2 = ADC_CR2_ADON;
/* Reset calibration just to be safe.*/
ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
;
/* Calibration.*/
ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
;
/* Return the ADC in low power mode.*/
ADC1->CR2 = 0;
rccDisableADC1(FALSE);
#endif
}
/**
* @brief Low level ADC driver initialization.
*
* @notapi
*/
void adc_lld_init(void) {
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
ADCD1.dmastp = STM32_DMA1_STREAM1;
ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
/* The shared vector is initialized on driver initialization and never
disabled.*/
nvicEnableVector(12, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
/* Calibration procedure.*/
rccEnableADC1(FALSE);
chDbgAssert(ADC1->CR == 0, "adc_lld_init(), #1", "invalid register state");
ADC1->CR |= ADC_CR_ADCAL;
while (ADC1->CR & ADC_CR_ADCAL)
;
rccDisableADC1(FALSE);
}
/**
* @brief Low level ADC driver initialization.
*
* @notapi
*/
void adc_lld_init(void) {
#if PLATFORM_ADC_USE_ADC1 == TRUE
/* Driver initialization.*/
adcObjectInit(&ADCD1);
#endif
}
/**
* @brief Low level ADC driver initialization.
*
* @notapi
*/
void adc_lld_init(void) {
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
#if defined(ADC1_2_COMMON)
ADCD1.adcc = ADC1_2_COMMON;
#else
ADCD1.adcc = ADC1_COMMON;
#endif
ADCD1.adcm = ADC1;
#if STM32_ADC_DUAL_MODE
ADCD1.adcs = ADC2;
#endif
ADCD1.dmastp = STM32_DMA1_STREAM1;
ADCD1.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
nvicEnableVector(ADC1_2_IRQn, STM32_ADC_ADC12_IRQ_PRIORITY);
#endif /* STM32_ADC_USE_ADC1 */
#if STM32_ADC_USE_ADC3
/* Driver initialization.*/
adcObjectInit(&ADCD3);
#if defined(ADC3_4_COMMON)
ADCD3.adcc = ADC3_4_COMMON;
#else
ADCD3.adcc = ADC3_COMMON;
#endif
ADCD3.adcm = ADC3;
#if STM32_ADC_DUAL_MODE
ADCD3.adcs = ADC4;
#endif
ADCD3.dmastp = STM32_DMA2_STREAM5;
ADCD3.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
nvicEnableVector(ADC3_IRQn, STM32_ADC_ADC34_IRQ_PRIORITY);
#if STM32_ADC_DUAL_MODE
nvicEnableVector(ADC4_IRQn, STM32_ADC_ADC34_IRQ_PRIORITY);
#endif
#endif /* STM32_ADC_USE_ADC3 */
}
/**
* @brief Low level ADC driver initialization.
*
* @notapi
*/
void adc_lld_init(void) {
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
ADCD1.dmastp = STM32_DMA1_STREAM1;
ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
/* The shared vector is initialized on driver initialization and never
disabled.*/
nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
}
/**
* @brief Low level ADC driver initialization.
*
* @notapi
*/
void adc_lld_init(void) {
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
#if STM32_ADC_USE_SDADC
ADCD1.sdadc = NULL;
#endif
ADCD1.dmastp = STM32_DMA1_STREAM1;
ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
nvicEnableVector(ADC1_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_ADC1_IRQ_PRIORITY));
#endif
#if STM32_ADC_USE_SDADC1
/* Driver initialization.*/
adcObjectInit(&SDADCD1);
#if STM32_ADC_USE_ADC
SDADCD1.adc = NULL;
#endif
SDADCD1.sdadc = SDADC1;
SDADCD1.dmastp = STM32_DMA2_STREAM3;
SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
nvicEnableVector(SDADC1_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_SDADC1_IRQ_PRIORITY));
#endif
#if STM32_ADC_USE_SDADC2
/* Driver initialization.*/
adcObjectInit(&SDADCD2);
#if STM32_ADC_USE_ADC
SDADCD2.adc = NULL;
#endif
SDADCD2.sdadc = SDADC2;
SDADCD2.dmastp = STM32_DMA2_STREAM4;
SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
nvicEnableVector(SDADC2_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_SDADC2_IRQ_PRIORITY));
#endif
#if STM32_ADC_USE_SDADC3
/* Driver initialization.*/
adcObjectInit(&SDADCD3);
#if STM32_ADC_USE_ADC
SDADCD3.adc = NULL;
#endif
SDADCD3.sdadc = SDADC3;
SDADCD3.dmastp = STM32_DMA2_STREAM5;
SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
nvicEnableVector(SDADC3_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_SDADC3_IRQ_PRIORITY));
#endif
}
/**
* @brief Low level ADC driver initialization.
*
* @notapi
*/
void adc_lld_init(void) {
clkmask = 0;
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
#if defined(ADC1_2_COMMON)
ADCD1.adcc = ADC1_2_COMMON;
#elif defined(ADC123_COMMON)
ADCD1.adcc = ADC123_COMMON;
#else
ADCD1.adcc = ADC1_COMMON;
#endif
ADCD1.adcm = ADC1;
#if STM32_ADC_DUAL_MODE
ADCD1.adcs = ADC2;
#endif
#if STM32_DMA_SUPPORTS_DMAMUX
ADCD1.dmastp = NULL;
#else
ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
#endif
ADCD1.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif /* STM32_ADC_USE_ADC1 */
#if STM32_ADC_USE_ADC2
/* Driver initialization.*/
adcObjectInit(&ADCD2);
#if defined(ADC1_2_COMMON)
ADCD2.adcc = ADC1_2_COMMON;
#elif defined(ADC123_COMMON)
ADCD2.adcc = ADC123_COMMON;
#endif
ADCD2.adcm = ADC2;
#if STM32_DMA_SUPPORTS_DMAMUX
ADCD2.dmastp = NULL;
#else
ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
#endif
ADCD2.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif /* STM32_ADC_USE_ADC2 */
#if STM32_ADC_USE_ADC3
/* Driver initialization.*/
adcObjectInit(&ADCD3);
#if defined(ADC3_4_COMMON)
ADCD3.adcc = ADC3_4_COMMON;
#elif defined(ADC123_COMMON)
ADCD3.adcc = ADC123_COMMON;
#else
ADCD3.adcc = ADC3_COMMON;
#endif
ADCD3.adcm = ADC3;
#if STM32_ADC_DUAL_MODE
ADCD3.adcs = ADC4;
#endif
#if STM32_DMA_SUPPORTS_DMAMUX
ADCD3.dmastp = NULL;
#else
ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
#endif
ADCD3.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif /* STM32_ADC_USE_ADC3 */
#if STM32_ADC_USE_ADC4
/* Driver initialization.*/
adcObjectInit(&ADCD4);
ADCD4.adcc = ADC3_4_COMMON;
ADCD4.adcm = ADC4;
#if STM32_DMA_SUPPORTS_DMAMUX
ADCD4.dmastp = NULL;
#else
ADCD4.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_STREAM);
#endif
ADCD4.dmamode = ADC_DMA_SIZE |
STM32_DMA_CR_PL(STM32_ADC_ADC4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif /* STM32_ADC_USE_ADC4 */
/* IRQs setup.*/
#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
nvicEnableVector(STM32_ADC1_NUMBER, STM32_ADC_ADC12_IRQ_PRIORITY);
#endif
#if STM32_ADC_USE_ADC3
nvicEnableVector(STM32_ADC3_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
#if STM32_ADC_DUAL_MODE
nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
#endif
#endif
#if STM32_ADC_USE_ADC4
nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);
#endif
/* ADC units pre-initializations.*/
#if defined(STM32F3XX)
#if STM32_HAS_ADC1 && STM32_HAS_ADC2
#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
rccEnableADC12(true);
rccResetADC12();
ADC1_2_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC12();
#endif
#else
#if STM32_ADC_USE_ADC1
rccEnableADC12(true);
rccResetADC12();
ADC1_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC12();
#endif
#endif
#if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4
rccEnableADC34(true);
rccResetADC34();
ADC3_4_COMMON->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC34();
#endif
#endif
#if defined(STM32L4XX) || defined(STM32L4XXP)
rccEnableADC123(true);
rccResetADC123();
#if defined(ADC1_2_COMMON)
ADC1_2_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
#elif defined(ADC123_COMMON)
ADC123_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
#else
ADC1_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
#endif
rccDisableADC123();
#endif
}
