/***************************************************************************//**
* @brief Initializes the AD9467 FPGA core.
*
* @param dco_delay - ADC delay.
*
* @return None.
*******************************************************************************/
void adc_setup(u32 dco_delay)
{
Xil_Out32((CF_BASEADDR + CF_REG_PN_TYPE), CF_PN_TYPE_BIT(0)); // Select PN9
Xil_Out32((CF_BASEADDR + CF_REG_DATA_SELECT), CF_DATA_SELECT_BIT(0)); // First byte from DDR appears on rising edge
Xil_Out32((CF_BASEADDR + CF_REG_DELAY_CTRL), 0x00000); // clear bits
Xil_Out32((CF_BASEADDR + CF_REG_DELAY_CTRL), CF_DELAY_CTRL_SEL(1) |
CF_DELAY_CTRL_WR_ADDR(0xF) | // delay write
CF_DELAY_CTRL_WR_DATA(0x1F));
Xil_Out32((CF_BASEADDR + CF_REG_DELAY_CTRL), CF_DELAY_CTRL_SEL(1) | // delay write
CF_DELAY_CTRL_WR_ADDR(0xF) |
CF_DELAY_CTRL_WR_DATA(0x1F));
ad9467_test_mode(5); // Select PN 23 sequence test mode
ad9467_output_format(0); // Select output format as offset binary
ad9467_transfer(); // Synchronously update registers
Xil_Out32((CF_BASEADDR + CF_REG_PN_TYPE), CF_PN_TYPE_BIT(1));
ad9467_dco_clock_invert(0); // Activates the non-inverted DCO clock
ad9467_transfer(); // Synchronously update registers
xil_printf("AD9467[REG_OUT_PHASE]: %02x\n\r", ad9467_dco_clock_invert(-1)); // reads the dco clock invert bit state
delay_ms(10);
if (adc_delay())
{
ad9467_dco_clock_invert(1); // Activates the inverted DCO clock
ad9467_transfer(); // Synchronously update registers
xil_printf("AD9467[REG_OUT_PHASE]: %02x\n\r",
ad9467_dco_clock_invert(-1)); // reads the dco clock invert bit state
delay_ms(10);
if (adc_delay())
{
xil_printf("adc_setup: can not set a zero error delay!\n\r");
adc_delay_1(0);
}
}
}
/***************************************************************************//**
* @brief Initializes the AD9467 FPGA core.
*
* @param dco_delay - ADC delay.
*
* @return None.
*******************************************************************************/
void adc_setup(uint32_t dco_delay)
{
Xil_Out32((CF_BASEADDR + 0x040), 0x3);
delay_ms(10);
// setup device
ad9467_write(AD9467_REG_TEST_IO, 0x05); // pn23
ad9467_write(AD9467_REG_DEVICE_UPDATE, 0x01); // update
ad9467_write(AD9467_REG_DEVICE_UPDATE, 0x00);
xil_printf("AD9467[0x016]: %02x\n\r", ad9467_read(AD9467_REG_OUT_PHASE));
// setup adc core
Xil_Out32((CF_BASEADDR+0x44), 0x2); // DDR_EDGESEL active
Xil_Out32((CF_BASEADDR+0x400), 0x3); // pn23
Xil_Out32((CF_BASEADDR+0x60), 0x0); // clear Delay Control
Xil_Out32((CF_BASEADDR+0x60), 0x20F1F); // Setup Delay Control
delay_ms(10);
if (adc_delay(8, 1)) {
xil_printf("AD9467[0x016]: %02x\n\r", ad9467_read(0x16));
ad9467_write(AD9467_REG_OUT_PHASE, 0x80);
ad9467_write(AD9467_REG_DEVICE_UPDATE, 0x01);
ad9467_write(AD9467_REG_DEVICE_UPDATE, 0x00);
xil_printf("AD9467[0x016]: %02x\n\r", ad9467_read(0x16));
delay_ms(10);
if (adc_delay(16, 1)) {
xil_printf("adc_setup: can not set a zero error delay!\n\r");
}
}
}
VOID
main (
VOID
)
{
uint16_t offset, gain;
analogin_init(&adc0, MBED_ADC_EXAMPLE_PIN_1); // no pinout on HDK board
analogin_init(&adc1, MBED_ADC_EXAMPLE_PIN_2);
analogin_init(&adc2, MBED_ADC_EXAMPLE_PIN_3);
#if ADC_CALIBRATION
sys_adc_calibration(0, &offset, &gain);
printf("ADC:offset = 0x%x, gain = 0x%x\n", offset, gain);
if((offset==0xFFFF) || (gain==0xFFFF))
#endif
{
offset = OFFSET;
gain = GAIN_DIV;
printf("ADC:offset = 0x%x, gain = 0x%x\n", offset, gain);
}
for (;;){
adcdat0 = analogin_read_u16(&adc0);
adcdat1 = analogin_read_u16(&adc1);
adcdat2 = analogin_read_u16(&adc2);
v_mv0 = AD2MV(adcdat0, offset, gain);
v_mv1 = AD2MV(adcdat1, offset, gain);
v_mv2 = AD2MV(adcdat2, offset, gain);
printf("AD0:%x = %d mv, AD1:%x = %d mv, AD2:%x = %d mv\n", adcdat0, v_mv0, adcdat1, v_mv1, adcdat2, v_mv2);
adc_delay();
}
analogin_deinit(&adc0);
analogin_deinit(&adc1);
analogin_deinit(&adc2);
}
static inline void ads8568_read_bus( uint16_t *data)
{
GPIO_setOutput( ADC_RD, GPIO_LOW );
adc_delay(1);
*data = adc_gpio_bus_data_convert(GPIO_getBank(GPIO_BANK0));
GPIO_setOutput( ADC_RD, GPIO_HIGH );
}
