void tshw_init(void)
{
rcc_periph_clock_enable(RCC_ADC1);
/* Make sure the ADC doesn't run during config. */
// adc_off(TS_ADC);
adc_set_dual_mode(ADC_CR1_DUALMOD_IND);
adc_set_single_conversion_mode(TS_ADC);
// adc_enable_trigger(TS_ADC, ADC_CR2_EXTSEL_SWSTART);
adc_set_right_aligned(TS_ADC);
tshw_prepare_wait();
delay(100);
}
void accel_highg_init()
{
uint8_t channel_array[16];
gpio_set_mode(GPIOB, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_ANALOG, GPIO0 | GPIO1 | GPIO2);
adc_set_dual_mode(ADC_CR1_DUALMOD_RSM);
/* ADC1 + ADC2 dual mode */
adc_set_dual_mode(ADC_CR1_DUALMOD_ISM);
adc_enable_external_trigger_injected(ADC1, ADC_CR2_JEXTSEL_TIM1_TRGO);
adc_enable_external_trigger_injected(ADC3, ADC_CR2_JEXTSEL_TIM1_TRGO);
adc_enable_dma(ADC1);
adc_enable_dma(ADC3);
adc_power_on(ADC1);
adc_power_on(ADC2);
adc_power_on(ADC3);
adc_stab_sleep();
adc_reset_calibration(ADC1);
adc_reset_calibration(ADC2);
adc_reset_calibration(ADC3);
adc_calibration(ADC1);
adc_calibration(ADC2);
adc_calibration(ADC3);
memset(channel_array, 0, sizeof(channel_array));
channel_array[0] = 10;
adc_set_injected_sequence(ADC1, 1, channel_array);
channel_array[0] = 11;
adc_set_injected_sequence(ADC2, 1, channel_array);
channel_array[0] = 12;
adc_set_injected_sequence(ADC3, 1, channel_array);
timer_reset(TIM1);
timer_enable_irq(TIM1, TIM_DIER_UIE);
timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* 500Hz */
timer_set_prescaler(TIM1, 64);
timer_set_period(TIM1, 2250);
/* Generate TRGO */
timer_set_master_mode(TIM1, TIM_CR2_MMS_UPDATE);
dma_set_peripheral_address(DMA1, DMA_CHANNEL5, (uint32_t) &ADC1_DR);
dma_set_read_from_memory(DMA1, DMA_CHANNEL5);
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL5);
dma_set_peripheral_size(DMA1, DMA_CHANNEL5, DMA_CCR_PSIZE_32BIT);
dma_set_memory_size(DMA1, DMA_CHANNEL5, DMA_CCR_MSIZE_32BIT);
dma_set_priority(DMA1, DMA_CHANNEL5, DMA_CCR_PL_HIGH);
dma_set_peripheral_address(DMA1, DMA_CHANNEL6, (uint32_t) &ADC3_DR);
dma_set_read_from_peripheral(DMA1, DMA_CHANNEL6);
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL6);
dma_set_peripheral_size(DMA1, DMA_CHANNEL6, DMA_CCR_PSIZE_16BIT);
dma_set_memory_size(DMA1, DMA_CHANNEL6, DMA_CCR_MSIZE_16BIT);
dma_set_priority(DMA1, DMA_CHANNEL6, DMA_CCR_PL_HIGH);
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL5);
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL6);
}
/**
* Initialize analog to digital converter
*/
void adc_init(adc_callback_t half_transfer_callback,
adc_callback_t transfer_complete_callback)
{
/* Reset adc_state. */
adc_state.dma_transfer_error_counter = 0;
adc_state.half_transfer_callback = half_transfer_callback;
adc_state.transfer_complete_callback = transfer_complete_callback;
/* Initialize peripheral clocks. */
rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA1EN);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC2EN);
/* Initialize the ADC input GPIO. */
/* WARNING: this code is written to work with strip. On the strip
* hardware we are lucky and all the ADC channels are on the same bank
* so we can initialize all of them in one go. This code will need to be
* changed/improved if we ever have to support hardware that has the
* ADC's spread over more then one bank.
*/
gpio_set_mode(ADC_BANK, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_ANALOG, ADC_PORT_U_VOLTAGE |
ADC_PORT_V_VOLTAGE |
ADC_PORT_W_VOLTAGE |
ADC_PORT_V_BATT |
ADC_PORT_CURRENT);
/* Configure DMA for data aquisition. */
/* Channel 1 reacts to: ADC1, TIM2_CH3 and TIM4_CH1 */
dma_channel_reset(DMA1, DMA_CHANNEL1);
dma_set_peripheral_address(DMA1, DMA_CHANNEL1, (uint32_t)&ADC1_DR);
dma_set_memory_address(DMA1, DMA_CHANNEL1,
(uint32_t)adc_state.raw_data);
dma_set_number_of_data(DMA1, DMA_CHANNEL1, ADC_RAW_SAMPLE_COUNT/2);
dma_set_read_from_peripheral(DMA1, DMA_CHANNEL1);
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL1);
dma_enable_circular_mode(DMA1, DMA_CHANNEL1);
dma_set_peripheral_size(DMA1, DMA_CHANNEL1, DMA_CCR_PSIZE_32BIT);
dma_set_memory_size(DMA1, DMA_CHANNEL1, DMA_CCR_MSIZE_32BIT);
dma_set_priority(DMA1, DMA_CHANNEL1, DMA_CCR_PL_VERY_HIGH);
dma_enable_half_transfer_interrupt(DMA1, DMA_CHANNEL1);
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL1);
dma_enable_transfer_error_interrupt(DMA1, DMA_CHANNEL1);
dma_enable_channel(DMA1, DMA_CHANNEL1);
/* Configure interrupts in NVIC. */
nvic_set_priority(NVIC_DMA1_CHANNEL1_IRQ, 0);
nvic_enable_irq(NVIC_DMA1_CHANNEL1_IRQ);
/* Disable ADC's. */
adc_off(ADC1);
adc_off(ADC2);
/* Enable dualmode. */
adc_set_dual_mode(ADC_CR1_DUALMOD_RSM); /* Dualmode regular only. */
/* Configure the adc channels. */
adc_config(ADC1, adc1_channel_array);
adc_config(ADC2, adc2_channel_array);
/* Start converting. */
adc_start_conversion_regular(ADC1);
}
