int init_ports(struct fpga_model* model, int dup_warn)
{
int x, y, i, j, k, row_num, row_pos, rc;
// inner and outer IO tiles (ILOGIC/ILOGIC/IODELAY)
for (x = LEFT_SIDE_WIDTH; x < model->x_width - RIGHT_SIDE_WIDTH; x++) {
if (has_device(model, TOP_OUTER_IO, x, DEV_ILOGIC)) {
rc = init_iologic_ports(model, TOP_OUTER_IO, x, TOP_S, dup_warn);
if (rc) goto xout;
}
if (has_device(model, TOP_INNER_IO, x, DEV_ILOGIC)) {
rc = init_iologic_ports(model, TOP_INNER_IO, x, TOP_S, dup_warn);
if (rc) goto xout;
}
if (has_device(model, model->y_height - BOT_INNER_IO, x, DEV_ILOGIC)) {
rc = init_iologic_ports(model, model->y_height - BOT_INNER_IO, x, BOTTOM_S, dup_warn);
if (rc) goto xout;
}
if (has_device(model, model->y_height - BOT_OUTER_IO, x, DEV_ILOGIC)) {
rc = init_iologic_ports(model, model->y_height - BOT_OUTER_IO, x, BOTTOM_S, dup_warn);
if (rc) goto xout;
}
}
for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
if (has_device(model, y, LEFT_IO_DEVS, DEV_ILOGIC)) {
rc = init_iologic_ports(model, y, LEFT_IO_DEVS, LEFT_S, dup_warn);
if (rc) goto xout;
}
if (has_device(model, y, model->x_width - RIGHT_IO_DEVS_O, DEV_ILOGIC)) {
rc = init_iologic_ports(model, y, model->x_width - RIGHT_IO_DEVS_O, RIGHT_S, dup_warn);
if (rc) goto xout;
}
}
for (x = 0; x < model->x_width; x++) {
// VCC, GND and fans
if (is_atx(X_ROUTING_COL, model, x)) {
for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
model, y))
continue;
rc = add_connpt_name(model, y, x, "VCC_WIRE",
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, "GND_WIRE",
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, "KEEP1_WIRE",
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, "FAN",
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, "FAN_B",
dup_warn, 0, 0);
if (rc) goto xout;
if (!is_atyx(YX_IO_ROUTING, model, y, x)) {
for (i = 0; i <= 1; i++) {
rc = add_connpt_name(model, y, x, pf("GFAN%i", i),
dup_warn, 0, 0);
if (rc) goto xout;
}
} else {
if (!is_atx(X_CENTER_ROUTING_COL, model, x)
|| is_aty(Y_TOPBOT_IO_RANGE, model, y)) {
// In the center those 2 wires are connected
// to the PLL, but elsewhere? Not clear what they
// connect to...
rc = add_connpt_name(model, y, x,
logicin_s(X_A5, 1 /* routing_io */),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x,
logicin_s(X_B4, 1 /* routing_io */),
dup_warn, 0, 0);
if (rc) goto xout;
}
}
}
}
// logicin
if (is_atx(X_FABRIC_LOGIC_XL_ROUTING_COL
|X_CENTER_ROUTING_COL, model, x)) {
for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
static const int n[] = { 36, 44, 53, 61, 62 };
if (is_aty(Y_TOPBOT_IO_RANGE, model, y)
&& !is_atx(X_ROUTING_NO_IO, model, x))
continue;
if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
model, y))
continue;
if (is_atx(X_CENTER_ROUTING_COL, model, x)
&& (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
model, y+1)
|| is_aty(Y_ROW_HORIZ_AXSYMM, model, y-1)))
continue;
for (i = 0; i < sizeof(n)/sizeof(*n); i++) {
rc = add_connpt_name(model, y, x,
pf("LOGICIN_B%i", n[i]), dup_warn, 0, 0);
if (rc) goto xout;
}
}
}
// bram
if (is_atx(X_FABRIC_BRAM_COL, model, x)) {
for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
if (YX_TILE(model, y, x)->flags & TF_BRAM_DEV) {
static const char* pass_str[3] = {"RAMB16BWER", "RAMB8BWER_0", "RAMB8BWER_1"};
// pass 0 is ramb16, pass 1 and 2 are for ramb8
for (i = 0; i <= 2; i++) {
for (j = 'A'; j <= 'B'; j++) {
rc = add_connpt_name(model, y, x, pf("%s_CLK%c", pass_str[i], j),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("%s_EN%c", pass_str[i], j),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("%s_REGCE%c", pass_str[i], j),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("%s_RST%c", pass_str[i], j),
dup_warn, 0, 0);
if (rc) goto xout;
for (k = 0; k <= (!i ? 3 : 1); k++) {
rc = add_connpt_name(model, y, x, pf("%s_DIP%c%i", pass_str[i], j, k),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("%s_DOP%c%i", pass_str[i], j, k),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("%s_WE%c%i", pass_str[i], j, k),
dup_warn, 0, 0);
if (rc) goto xout;
}
for (k = 0; k <= (!i ? 13 : 12); k++) {
rc = add_connpt_name(model, y, x, pf("%s_ADDR%c%i", pass_str[i], j, k),
dup_warn, 0, 0);
if (rc) goto xout;
}
for (k = 0; k <= (!i ? 31 : 15); k++) {
rc = add_connpt_name(model, y, x, pf("%s_DI%c%i", pass_str[i], j, k),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("%s_DO%c%i", pass_str[i], j, k),
dup_warn, 0, 0);
if (rc) goto xout;
}
}
}
}
}
}
// macc
if (is_atx(X_FABRIC_MACC_COL, model, x)) {
for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
if (YX_TILE(model, y, x)->flags & TF_MACC_DEV) {
static const char* pref[] = {"CE", "RST", ""};
static const char* seq[] = {"A", "B", "C", "D", "M", "P", "OPMODE", ""};
is_in_row(model, y, &row_num, &row_pos);
if (!row_num && row_pos == LAST_POS_IN_ROW) {
rc = add_connpt_name(model, y, x, "CARRYIN_DSP48A1_SITE",
dup_warn, 0, 0);
if (rc) goto xout;
for (i = 0; i <= 47; i++) {
rc = add_connpt_name(model, y, x, pf("PCIN%i_DSP48A1_SITE", i),
dup_warn, 0, 0);
if (rc) goto xout;
}
}
rc = add_connpt_name(model, y, x, "CLK_DSP48A1_SITE",
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, "CARRYOUT_DSP48A1_SITE",
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, "CARRYOUTF_DSP48A1_SITE",
dup_warn, 0, 0);
if (rc) goto xout;
for (i = 0; pref[i][0]; i++) {
rc = add_connpt_name(model, y, x, pf("%sCARRYIN_DSP48A1_SITE", pref[i]),
dup_warn, 0, 0);
if (rc) goto xout;
for (j = 0; seq[j][0]; j++) {
rc = add_connpt_name(model, y, x, pf("%s%s_DSP48A1_SITE", pref[i], seq[j]),
dup_warn, 0, 0);
if (rc) goto xout;
}
}
for (i = 0; i <= 17; i++) {
rc = add_connpt_name(model, y, x, pf("A%i_DSP48A1_SITE", i),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("B%i_DSP48A1_SITE", i),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("D%i_DSP48A1_SITE", i),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("BCOUT%i_DSP48A1_SITE", i),
dup_warn, 0, 0);
if (rc) goto xout;
}
for (i = 0; i <= 47; i++) {
rc = add_connpt_name(model, y, x, pf("C%i_DSP48A1_SITE", i),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("P%i_DSP48A1_SITE", i),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("PCOUT%i_DSP48A1_SITE", i),
dup_warn, 0, 0);
if (rc) goto xout;
}
for (i = 0; i <= 35; i++) {
rc = add_connpt_name(model, y, x, pf("M%i_DSP48A1_SITE", i),
dup_warn, 0, 0);
if (rc) goto xout;
}
for (i = 0; i <= 7; i++) {
rc = add_connpt_name(model, y, x, pf("OPMODE%i_DSP48A1_SITE", i),
dup_warn, 0, 0);
if (rc) goto xout;
}
}
}
}
}
return 0;
xout:
return rc;
}
static int init_logic(struct fpga_model* model, int y, int x, int idx)
{
struct fpga_tile* tile;
const char* pre;
int i, j, rc;
RC_CHECK(model);
tile = YX_TILE(model, y, x);
if (tile->devs[idx].subtype == LOGIC_M)
pre = "M_";
else if (tile->devs[idx].subtype == LOGIC_L)
pre = "L_";
else if (tile->devs[idx].subtype == LOGIC_X) {
pre = is_atx(X_FABRIC_LOGIC_XL_COL|X_CENTER_LOGIC_COL, model, x)
? "XX_" : "X_";
} else FAIL(EINVAL);
tile->devs[idx].pinw = calloc((LO_LAST+1)
*sizeof(tile->devs[idx].pinw[0]), /*elsize*/ 1);
if (!tile->devs[idx].pinw) FAIL(ENOMEM);
tile->devs[idx].num_pinw_total = LO_LAST+1;
tile->devs[idx].num_pinw_in = LI_LAST+1;
for (i = 0; i < 4; i++) { // 'A' to 'D'
for (j = 0; j < 6; j++) {
rc = add_connpt_name(model, y, x, pf("%s%c%i", pre, 'A'+i, j+1),
/*dup_warn*/ 1,
&tile->devs[idx].pinw[LI_A1+i*6+j], 0);
if (rc) FAIL(rc);
}
rc = add_connpt_name(model, y, x, pf("%s%cX", pre, 'A'+i),
/*dup_warn*/ 1,
&tile->devs[idx].pinw[LI_AX+i], 0);
if (rc) FAIL(rc);
if (tile->devs[idx].subtype == LOGIC_M) {
rc = add_connpt_name(model, y, x, pf("%s%cI", pre, 'A'+i),
/*dup_warn*/ 1,
&tile->devs[idx].pinw[LI_AI+i], 0);
if (rc) FAIL(rc);
} else
tile->devs[idx].pinw[LI_AI+i] = STRIDX_NO_ENTRY;
rc = add_connpt_name(model, y, x, pf("%s%c", pre, 'A'+i),
/*dup_warn*/ 1,
&tile->devs[idx].pinw[LO_A+i], 0);
if (rc) FAIL(rc);
rc = add_connpt_name(model, y, x, pf("%s%cMUX", pre, 'A'+i),
/*dup_warn*/ 1,
&tile->devs[idx].pinw[LO_AMUX+i], 0);
if (rc) FAIL(rc);
rc = add_connpt_name(model, y, x, pf("%s%cQ", pre, 'A'+i),
/*dup_warn*/ 1,
&tile->devs[idx].pinw[LO_AQ+i], 0);
if (rc) FAIL(rc);
}
rc = add_connpt_name(model, y, x, pf("%sCLK", pre),
/*dup_warn*/ 1,
&tile->devs[idx].pinw[LI_CLK], 0);
if (rc) FAIL(rc);
rc = add_connpt_name(model, y, x, pf("%sCE", pre),
/*dup_warn*/ 1,
&tile->devs[idx].pinw[LI_CE], 0);
if (rc) FAIL(rc);
rc = add_connpt_name(model, y, x, pf("%sSR", pre),
/*dup_warn*/ 1,
&tile->devs[idx].pinw[LI_SR], 0);
if (rc) FAIL(rc);
if (tile->devs[idx].subtype == LOGIC_M) {
rc = add_connpt_name(model, y, x, pf("%sWE", pre),
/*dup_warn*/ 1,
&tile->devs[idx].pinw[LI_WE], 0);
if (rc) FAIL(rc);
} else
tile->devs[idx].pinw[LI_WE] = STRIDX_NO_ENTRY;
if (tile->devs[idx].subtype != LOGIC_X) {
// Wire connections will go to some CIN later
// (and must not warn about duplicates), but we
// have to add the connection point here so
// that pinw[LI_CIN] is initialized.
rc = add_connpt_name(model, y, x, pf("%sCIN", pre),
/*dup_warn*/ 1,
&tile->devs[idx].pinw[LI_CIN], 0);
if (rc) FAIL(rc);
} else
tile->devs[idx].pinw[LI_CIN] = STRIDX_NO_ENTRY;
if (tile->devs[idx].subtype == LOGIC_M) {
rc = add_connpt_name(model, y, x, "M_COUT",
/*dup_warn*/ 1,
&tile->devs[idx].pinw[LO_COUT], 0);
if (rc) FAIL(rc);
} else if (tile->devs[idx].subtype == LOGIC_L) {
rc = add_connpt_name(model, y, x, "XL_COUT",
/*dup_warn*/ 1,
&tile->devs[idx].pinw[LO_COUT], 0);
if (rc) FAIL(rc);
} else
tile->devs[idx].pinw[LO_COUT] = STRIDX_NO_ENTRY;
return 0;
fail:
return rc;
}
static int init_iologic_ports(struct fpga_model* model, int y, int x,
enum which_side side, int dup_warn)
{
static const char* prefix, *suffix1, *suffix2;
int rc, i;
switch (side) {
case TOP_S: prefix = "TIOI"; break;
case BOTTOM_S: prefix = "BIOI"; break;
case LEFT_S: prefix = "LIOI"; break;
case RIGHT_S: prefix = "RIOI"; break;
default: EXIT(1);
}
if (side == LEFT_S || side == RIGHT_S) {
suffix1 = "_M";
suffix2 = "_S";
} else {
suffix1 = "_STUB";
suffix2 = "_S_STUB";
}
for (i = X_A /* 0 */; i <= M_DQ /* 23 */; i++) {
rc = add_connpt_name(model, y, x, pf("IOI_INTER_LOGICOUT%i", i),
dup_warn, /*name_i*/ 0, /*connpt_o*/ 0);
if (rc) goto xout;
}
rc = add_connpt_name(model, y, x, pf("%s_GND_TIEOFF", prefix),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("%s_VCC_TIEOFF", prefix),
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, pf("%s_KEEP1_STUB", prefix),
dup_warn, 0, 0);
if (rc) goto xout;
for (i = 0; i <= 4; i++) {
rc = add_connpt_2(model, y, x, pf("AUXADDR%i_IODELAY", i),
suffix1, suffix2, dup_warn);
if (rc) goto xout;
}
rc = add_connpt_2(model, y, x, "AUXSDOIN_IODELAY", suffix1, suffix2,
dup_warn);
if (rc) goto xout;
rc = add_connpt_2(model, y, x, "AUXSDO_IODELAY", suffix1, suffix2,
dup_warn);
if (rc) goto xout;
rc = add_connpt_2(model, y, x, "MEMUPDATE_IODELAY", suffix1, suffix2,
dup_warn);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, "OUTN_IODELAY_SITE",
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, "STUB_OUTN_IODELAY_S",
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, "OUTP_IODELAY_SITE",
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, "STUB_OUTP_IODELAY_S",
dup_warn, 0, 0);
if (rc) goto xout;
for (i = 1; i <= 4; i++) {
rc = add_connpt_2(model, y, x, pf("Q%i_ILOGIC_SITE", i), "", "_S",
dup_warn);
if (rc) goto xout;
rc = add_connpt_2(model, y, x, pf("D%i_OLOGIC_SITE", i), "", "_S",
dup_warn);
if (rc) goto xout;
rc = add_connpt_2(model, y, x, pf("T%i_OLOGIC_SITE", i), "", "_S",
dup_warn);
if (rc) goto xout;
rc = add_connpt_2(model, y, x, pf("SHIFTIN%i_OLOGIC_SITE", i), "", "_S",
dup_warn);
if (rc) goto xout;
rc = add_connpt_2(model, y, x, pf("SHIFTOUT%i_OLOGIC_SITE", i), "", "_S",
dup_warn);
if (rc) goto xout;
}
for (i = 0; i <= 1; i++) {
rc = add_connpt_2(model, y, x, pf("CFB%i_ILOGIC_SITE", i), "", "_S",
dup_warn);
if (rc) goto xout;
rc = add_connpt_2(model, y, x, pf("CLK%i_ILOGIC_SITE", i), "", "_S",
dup_warn);
if (rc) goto xout;
rc = add_connpt_2(model, y, x, pf("CLK%i_OLOGIC_SITE", i), "", "_S",
dup_warn);
if (rc) goto xout;
}
{
static const char* mcb_2[] = {
"BITSLIP_ILOGIC_SITE", "BUSY_IODELAY_SITE",
"CAL_IODELAY_SITE", "CE0_ILOGIC_SITE",
"CE_IODELAY_SITE", "CIN_IODELAY_SITE",
"CLKDIV_ILOGIC_SITE", "CLKDIV_OLOGIC_SITE",
"CLK_IODELAY_SITE", "DATAOUT_IODELAY_SITE",
"DDLY2_ILOGIC_SITE", "DDLY_ILOGIC_SITE",
"DFB_ILOGIC_SITE", "D_ILOGIC_IDATAIN_IODELAY",
"D_ILOGIC_SITE", "DOUT_IODELAY_SITE",
"FABRICOUT_ILOGIC_SITE", "IDATAIN_IODELAY_SITE",
"INCDEC_ILOGIC_SITE", "INC_IODELAY_SITE",
"IOCE_ILOGIC_SITE", "IOCE_OLOGIC_SITE",
"IOCLK1_IODELAY_SITE", "IOCLK_IODELAY_SITE",
"LOAD_IODELAY_SITE", "OCE_OLOGIC_SITE",
"ODATAIN_IODELAY_SITE", "OFB_ILOGIC_SITE",
"OQ_OLOGIC_SITE", "RCLK_IODELAY_SITE",
"READEN_IODELAY_UNUSED_SITE", "REV_ILOGIC_SITE",
"REV_OLOGIC_SITE", "RST_IODELAY_SITE",
"SHIFTIN_ILOGIC_SITE", "SHIFTOUT_ILOGIC_SITE",
"SR_ILOGIC_SITE", "SR_OLOGIC_SITE",
"TCE_OLOGIC_SITE", "TFB_ILOGIC_SITE",
"T_IODELAY_SITE", "TOUT_IODELAY_SITE",
"TQ_OLOGIC_SITE", "TRAIN_OLOGIC_SITE",
"VALID_ILOGIC_SITE", "" };
for (i = 0; mcb_2[i][0]; i++) {
rc = add_connpt_2(model, y, x, mcb_2[i], "", "_S",
dup_warn);
}
}
rc = add_connpt_name(model, y, x, "DATAOUT2_IODELAY_SITE",
dup_warn, 0, 0);
if (rc) goto xout;
rc = add_connpt_name(model, y, x, "DATAOUT2_IODELAY2_SITE_S",
dup_warn, 0, 0);
if (rc) goto xout;
for (i = 0; i <= 2; i++) {
rc = add_connpt_2(model, y, x, pf("IOI_CLK%iINTER", i),
"_M", "_S", dup_warn);
if (rc) goto xout;
}
for (i = 0; i <= 1; i++) {
rc = add_connpt_2(model, y, x, pf("IOI_CLKDIST_IOCE%i", i),
"_M", "_S", dup_warn);
if (rc) goto xout;
}
rc = add_connpt_2(model, y, x, "IOI_CLKDIST_CLK0_ILOGIC", "_M", "_S",
dup_warn);
if (rc) goto xout;
rc = add_connpt_2(model, y, x, "IOI_CLKDIST_CLK0_OLOGIC", "_M", "_S",
dup_warn);
if (rc) goto xout;
rc = add_connpt_2(model, y, x, "IOI_CLKDIST_CLK1", "_M", "_S",
dup_warn);
if (rc) goto xout;
if (side == TOP_S || side == BOTTOM_S) {
static const char* mcb_2[] = {
"IOI_MCB_DQIEN", "IOI_MCB_INBYP",
"IOI_MCB_IN", "IOI_MCB_OUTN",
"IOI_MCB_OUTP", "" };
static const char* mcb_1[] = {
"IOI_MCB_DRPADD", "IOI_MCB_DRPBROADCAST",
"IOI_MCB_DRPCLK", "IOI_MCB_DRPCS",
"IOI_MCB_DRPSDI", "IOI_MCB_DRPSDO",
"IOI_MCB_DRPTRAIN", "" };
for (i = 0; mcb_2[i][0]; i++) {
rc = add_connpt_2(model, y, x, mcb_2[i], "_M", "_S",
dup_warn);
if (rc) goto xout;
}
for (i = 0; mcb_1[i][0]; i++) {
rc = add_connpt_name(model, y, x, mcb_1[i],
dup_warn, 0, 0);
if (rc) goto xout;
}
}
return 0;
xout:
return rc;
}
static int init_iob(struct fpga_model* model, int y, int x, int idx)
{
struct fpga_tile* tile;
const char* prefix;
int type_idx, rc;
char tmp_str[128];
RC_CHECK(model);
tile = YX_TILE(model, y, x);
type_idx = fdev_typeidx(model, y, x, idx);
if (!y)
prefix = "TIOB";
else if (y == model->y_height - BOT_OUTER_ROW)
prefix = "BIOB";
else if (x == 0)
prefix = "LIOB";
else if (x == model->x_width - RIGHT_OUTER_O)
prefix = "RIOB";
else
FAIL(EINVAL);
tile->devs[idx].pinw = calloc((IOB_LAST_OUTPUT_PINW+1)
*sizeof(tile->devs[idx].pinw[0]), /*elsize*/ 1);
if (!tile->devs[idx].pinw) FAIL(ENOMEM);
tile->devs[idx].num_pinw_total = IOB_LAST_OUTPUT_PINW+1;
tile->devs[idx].num_pinw_in = IOB_LAST_INPUT_PINW+1;
snprintf(tmp_str, sizeof(tmp_str), "%s_O%i_PINW", prefix, type_idx);
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
&tile->devs[idx].pinw[IOB_IN_O], 0);
if (rc) FAIL(rc);
snprintf(tmp_str, sizeof(tmp_str), "%s_T%i_PINW", prefix, type_idx);
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
&tile->devs[idx].pinw[IOB_IN_T], 0);
if (rc) FAIL(rc);
snprintf(tmp_str, sizeof(tmp_str), "%s_DIFFI_IN%i", prefix, type_idx);
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
&tile->devs[idx].pinw[IOB_IN_DIFFI_IN], 0);
if (rc) FAIL(rc);
snprintf(tmp_str, sizeof(tmp_str), "%s_DIFFO_IN%i", prefix, type_idx);
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
&tile->devs[idx].pinw[IOB_IN_DIFFO_IN], 0);
if (rc) FAIL(rc);
snprintf(tmp_str, sizeof(tmp_str), "%s_IBUF%i_PINW", prefix, type_idx);
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
&tile->devs[idx].pinw[IOB_OUT_I], 0);
if (rc) FAIL(rc);
snprintf(tmp_str, sizeof(tmp_str), "%s_PADOUT%i", prefix, type_idx);
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
&tile->devs[idx].pinw[IOB_OUT_PADOUT], 0);
if (rc) FAIL(rc);
snprintf(tmp_str, sizeof(tmp_str), "%s_DIFFO_OUT%i", prefix, type_idx);
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
&tile->devs[idx].pinw[IOB_OUT_DIFFO_OUT], 0);
if (rc) FAIL(rc);
if (!x && y == model->center_y - CENTER_TOP_IOB_O && type_idx == 1)
strcpy(tmp_str, "LIOB_TOP_PCI_RDY0");
else if (!x && y == model->center_y + CENTER_BOT_IOB_O && type_idx == 0)
strcpy(tmp_str, "LIOB_BOT_PCI_RDY0");
else if (x == model->x_width-RIGHT_OUTER_O && y == model->center_y - CENTER_TOP_IOB_O && type_idx == 0)
strcpy(tmp_str, "RIOB_BOT_PCI_RDY0");
else if (x == model->x_width-RIGHT_OUTER_O && y == model->center_y + CENTER_BOT_IOB_O && type_idx == 1)
strcpy(tmp_str, "RIOB_TOP_PCI_RDY1");
else {
snprintf(tmp_str, sizeof(tmp_str),
"%s_PCI_RDY%i", prefix, type_idx);
}
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
&tile->devs[idx].pinw[IOB_OUT_PCI_RDY], 0);
if (rc) FAIL(rc);
return 0;
fail:
return rc;
}
