int lmi_flash_erase(struct target_s *target, uint32_t addr, int len)
{
ADIv5_AP_t *ap = adiv5_target_ap(target);
uint32_t tmp;
addr &= 0xFFFFFC00;
len &= 0xFFFFFC00;
/* setup word access */
adiv5_ap_write(ap, 0x00, 0xA2000052);
/* select Flash Control */
adiv5_dp_low_access(ap->dp, 1, 0, 0x04, 0x400FD000);
while(len) {
/* write address to FMA */
adiv5_ap_write(ap, 0x10, addr); /* Required to switch banks */
/* set ERASE bit in FMC */
adiv5_dp_low_access(ap->dp, 1, 0, 0x08, 0xA4420002);
/* Read FMC to poll for ERASE bit */
adiv5_dp_low_access(ap->dp, 1, 1, 0x08, 0);
do {
tmp = adiv5_dp_low_access(ap->dp, 1, 1, 0x08, 0);
} while (tmp & 2);
len -= 0x400;
addr += 0x400;
}
return 0;
}
static uint32_t apb_read(target *t, uint16_t reg)
{
struct cortexa_priv *priv = t->priv;
ADIv5_AP_t *ap = priv->apb;
uint32_t addr = priv->base + 4*reg;
adiv5_ap_write(ap, ADIV5_AP_TAR, addr);
adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0);
return adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0);
}
static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
{
if (addr & ADIV5_APnDP) {
adiv5_dp_low_access(dp, ADIV5_LOW_READ, addr, 0);
return adiv5_dp_low_access(dp, ADIV5_LOW_READ,
ADIV5_DP_RDBUFF, 0);
} else {
return adiv5_swdp_low_access(dp, ADIV5_LOW_READ, addr, 0);
}
}
static void apb_write(target *t, uint16_t reg, uint32_t val)
{
struct cortexa_priv *priv = t->priv;
ADIv5_AP_t *ap = priv->apb;
uint32_t addr = priv->base + 4*reg;
adiv5_ap_write(ap, ADIV5_AP_TAR, addr);
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DRW, val);
}
