void systick_init(void) { int i_state = interrupts_get_and_disable(); aic_mask_off(LOW_PRIORITY_IRQ); aic_set_vector(LOW_PRIORITY_IRQ, (1 << 5) /* positive internal edge */ | AIC_INT_LEVEL_LOW, (U32) tpl_primary_irq_handler);// (U32) systick_low_priority_entry); aic_mask_on(LOW_PRIORITY_IRQ); aic_mask_off(AT91C_PERIPHERAL_ID_SYSIRQ); aic_set_vector(AT91C_PERIPHERAL_ID_SYSIRQ, (1 << 5) /* positive internal edge */ | AIC_INT_LEVEL_NORMAL, (U32) tpl_primary_irq_handler);//(U32) systick_isr_entry); aic_mask_on(AT91C_PERIPHERAL_ID_SYSIRQ); *AT91C_PITC_PIMR = ((CLOCK_FREQUENCY / 16 / PIT_FREQ) - 1) | 0x03000000; /* Enable, enable interrupts */ if (i_state) interrupts_enable(); }
void nxt_spi_init(void) { int i_state = interrupts_get_and_disable(); #define SPI_BITRATE 2000000 *AT91C_PMC_PCER = (1L << AT91C_ID_SPI); /* Enable MCK clock */ *AT91C_PIOA_PER = AT91C_PIO_PA12;/*EnableA0onPA12*/ *AT91C_PIOA_OER = AT91C_PIO_PA12; *AT91C_PIOA_CODR = AT91C_PIO_PA12; *AT91C_PIOA_PDR = AT91C_PA14_SPCK;/*EnableSPCKonPA14*/ *AT91C_PIOA_ASR = AT91C_PA14_SPCK; *AT91C_PIOA_ODR = AT91C_PA14_SPCK; *AT91C_PIOA_OWER = AT91C_PA14_SPCK; *AT91C_PIOA_MDDR = AT91C_PA14_SPCK; *AT91C_PIOA_PPUDR = AT91C_PA14_SPCK; *AT91C_PIOA_IFDR = AT91C_PA14_SPCK; *AT91C_PIOA_CODR = AT91C_PA14_SPCK; *AT91C_PIOA_IDR = AT91C_PA14_SPCK; *AT91C_PIOA_PDR = AT91C_PA13_MOSI;/*EnablemosionPA13*/ *AT91C_PIOA_ASR = AT91C_PA13_MOSI; *AT91C_PIOA_ODR = AT91C_PA13_MOSI; *AT91C_PIOA_OWER = AT91C_PA13_MOSI; *AT91C_PIOA_MDDR = AT91C_PA13_MOSI; *AT91C_PIOA_PPUDR = AT91C_PA13_MOSI; *AT91C_PIOA_IFDR = AT91C_PA13_MOSI; *AT91C_PIOA_CODR = AT91C_PA13_MOSI; *AT91C_PIOA_IDR = AT91C_PA13_MOSI; *AT91C_PIOA_PDR = AT91C_PA10_NPCS2;/*Enablenpcs0onPA10*/ *AT91C_PIOA_BSR = AT91C_PA10_NPCS2; *AT91C_PIOA_ODR = AT91C_PA10_NPCS2; *AT91C_PIOA_OWER = AT91C_PA10_NPCS2; *AT91C_PIOA_MDDR = AT91C_PA10_NPCS2; *AT91C_PIOA_PPUDR = AT91C_PA10_NPCS2; *AT91C_PIOA_IFDR = AT91C_PA10_NPCS2; *AT91C_PIOA_CODR = AT91C_PA10_NPCS2; *AT91C_PIOA_IDR = AT91C_PA10_NPCS2; *AT91C_SPI_CR = AT91C_SPI_SWRST;/*Softreset*/ *AT91C_SPI_CR = AT91C_SPI_SPIEN;/*Enablespi*/ *AT91C_SPI_MR = AT91C_SPI_MSTR|AT91C_SPI_MODFDIS | (0xB<<16); AT91C_SPI_CSR[2] = ((CLOCK_FREQUENCY/SPI_BITRATE)<<8) | AT91C_SPI_CPOL; /* Set mode to unknown */ mode = 0xff; /* Set up safe dma refresh state */ data = display = (U8 *) 0; dirty = 0; page = 0; /* Install the interrupt handler */ aic_mask_off(AT91C_ID_SPI); aic_set_vector(AT91C_ID_SPI, AIC_INT_LEVEL_NORMAL, spi_isr_entry); aic_mask_on(AT91C_ID_SPI); *AT91C_SPI_PTCR = AT91C_PDC_TXTEN; if (i_state) interrupts_enable(); }
// Initialise the module void i2c_init(void) { int i; int istate; U32 dummy; for (i = 0; i < I2C_N_PORTS; i++) { i2c_ports[i] = NULL; } istate = interrupts_get_and_disable(); /* Set up Timer Counter 0 */ *AT91C_PMC_PCER = (1 << AT91C_ID_TC0); /* Power enable */ *AT91C_TC0_CCR = AT91C_TC_CLKDIS; /* Disable */ *AT91C_TC0_IDR = ~0; dummy = *AT91C_TC0_SR; *AT91C_TC0_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK|AT91C_TC_CPCTRG; /* MCLK/2, RC compare trigger */ *AT91C_TC0_RC = (CLOCK_FREQUENCY/2)/(2 * I2C_CLOCK); *AT91C_TC0_IER = AT91C_TC_CPCS; aic_mask_off(AT91C_ID_TC0); aic_set_vector(AT91C_ID_TC0, AIC_INT_LEVEL_NORMAL, (int)i2c_timer_isr_entry); aic_mask_on(AT91C_ID_TC0); if(istate) interrupts_enable(); }
int uart_us0_init_irq(void) { int i_state; U32 isr; isr = (U32) uart_isr_entry_0; i_state = interrupts_get_and_disable(); *AT91C_US0_IDR = 0xFFFFFFFF; // Set up UART(0) interrupt aic_mask_off(AT91C_PERIPHERAL_ID_US0); aic_set_vector(AT91C_PERIPHERAL_ID_US0, AIC_INT_LEVEL_NORMAL, isr); aic_mask_on(AT91C_PERIPHERAL_ID_US0); //*AT91C_US0_IER = 1; // Enable rx and tx interrupts. This should cause a bogus tx int //if (i_state) // interrupts_enable(); return i_state; }
void bt_init(void) { U8 trash; U32 trash2; in_buf_in_ptr = out_buf_ptr = 0; in_buf_idx = 0; *AT91C_PMC_PCER = (1 << AT91C_PERIPHERAL_ID_US1); *AT91C_PIOA_PDR = BT_RX_PIN | BT_TX_PIN | BT_SCK_PIN | BT_RTS_PIN | BT_CTS_PIN; *AT91C_PIOA_ASR = BT_RX_PIN | BT_TX_PIN | BT_SCK_PIN | BT_RTS_PIN | BT_CTS_PIN; *AT91C_US1_CR = AT91C_US_RSTSTA; *AT91C_US1_CR = AT91C_US_STTTO; *AT91C_US1_RTOR = 10000; *AT91C_US1_IDR = AT91C_US_TIMEOUT; *AT91C_US1_MR = (AT91C_US_USMODE_HWHSH & ~AT91C_US_SYNC) | AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT | AT91C_US_OVER; *AT91C_US1_BRGR = ((CLOCK_RATE/8/BAUD_RATE) | (((CLOCK_RATE/8) - ((CLOCK_RATE/8/BAUD_RATE) * BAUD_RATE)) / ((BAUD_RATE + 4)/8)) << 16); *AT91C_US1_PTCR = (AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); *AT91C_US1_RCR = 0; *AT91C_US1_TCR = 0; *AT91C_US1_RNPR = 0; *AT91C_US1_TNPR = 0; aic_mask_off(AT91C_PERIPHERAL_ID_US1); aic_clear(AT91C_PERIPHERAL_ID_US1); trash = *AT91C_US1_RHR; trash = *AT91C_US1_CSR; *AT91C_US1_RPR = (unsigned int)&(in_buf[0][0]); *AT91C_US1_RCR = 128; *AT91C_US1_RNPR = (unsigned int)&(in_buf[1][0]); *AT91C_US1_RNCR = 128; *AT91C_US1_CR = AT91C_US_RXEN | AT91C_US_TXEN; *AT91C_US1_PTCR = (AT91C_PDC_RXTEN | AT91C_PDC_TXTEN); *AT91C_PIOA_PDR = BT_RX_PIN | BT_TX_PIN | BT_SCK_PIN | BT_RTS_PIN | BT_CTS_PIN; *AT91C_PIOA_ASR = BT_RX_PIN | BT_TX_PIN | BT_SCK_PIN | BT_RTS_PIN | BT_CTS_PIN; *AT91C_PIOA_PER = BT_CS_PIN | BT_RST_PIN; *AT91C_PIOA_OER = BT_CS_PIN | BT_RST_PIN; *AT91C_PIOA_SODR = BT_CS_PIN | BT_RST_PIN; *AT91C_PIOA_PPUDR = BT_ARM7_CMD_PIN; *AT91C_PIOA_PER = BT_ARM7_CMD_PIN; *AT91C_PIOA_CODR = BT_ARM7_CMD_PIN; *AT91C_PIOA_OER = BT_ARM7_CMD_PIN; // Configure timer 01 as trigger for ADC, sample every 0.5ms *AT91C_PMC_PCER = (1 << AT91C_PERIPHERAL_ID_TC1); *AT91C_TC1_CCR = AT91C_TC_CLKDIS; *AT91C_TC1_IDR = ~0; trash2 = *AT91C_TC1_SR; *AT91C_TC1_CMR = AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR | AT91C_TC_ASWTRG_SET; /* MCLK/2, wave mode 10 */ *AT91C_TC1_RC = (CLOCK_FREQUENCY/2)/(2000); *AT91C_TC1_RA = (CLOCK_FREQUENCY/2)/(4000); *AT91C_TC1_CCR = AT91C_TC_CLKEN; *AT91C_TC1_CCR = AT91C_TC_SWTRG; *AT91C_PMC_PCER = (1 << AT91C_PERIPHERAL_ID_ADC); *AT91C_ADC_MR = 0; *AT91C_ADC_MR |= AT91C_ADC_TRGEN_EN | AT91C_ADC_TRGSEL_TIOA1; *AT91C_ADC_MR |= 0x00003F00; *AT91C_ADC_MR |= 0x00020000; *AT91C_ADC_MR |= 0x09000000; *AT91C_ADC_CHER = AT91C_ADC_CH6 | AT91C_ADC_CH4; buf_ptr = &(in_buf[0][0]); }
void systick_suspend() { aic_mask_off(LOW_PRIORITY_IRQ); }
int uart_init(U32 u, U32 baudRate, U32 dataBits, U32 stopBits, char parity) { struct soft_uart *p = &uart[u]; volatile struct _AT91S_USART *up; int i_state; U32 peripheral_id; U32 mode; U8 dummy; U32 isr; U32 pinmask = 0; int error = 0; if (u >= N_UARTS) return 0; p = &uart[u]; /* Initialise the uart structure */ switch (u) { case 0: p->uart = AT91C_BASE_US0; peripheral_id = AT91C_PERIPHERAL_ID_US0; pinmask = (1 << 5) | (1 << 6); isr = (U32) uart_isr_entry_0; break; case 1: p->uart = AT91C_BASE_US1; peripheral_id = AT91C_PERIPHERAL_ID_US1; pinmask = (1 << 21) | (1 << 22); // todo isr = (U32) uart_isr_entry_1; break; default: return 0; } byte_fifo_init(&p->tx, &tx_buffer[u][0], TX_FIFO_SIZE); byte_fifo_init(&p->rx, &rx_buffer[u][0], RX_FIFO_SIZE); p->transmitting = 0; up = p->uart; mode = 0; switch (dataBits) { case 7: mode |= 0x80; break; case 8: mode |= 0xc0; break; default: error = 1; } switch (stopBits) { case 1: mode |= 0x00000000; break; case 15: mode |= 0x00001000; break; case 2: mode |= 0x00002000; break; default: error = 1; } switch (parity) { case 'N': mode |= 0x00000800; break; case 'O': mode |= 0x00000200; break; case 'E': mode |= 0x00000000; break; case 'M': mode |= 0x00000600; break; case 'S': mode |= 0x00000400; break; default: error = 1; } if (error) return 0; i_state = interrupts_get_and_disable(); /* Grab the clock we need */ *AT91C_PMC_PCER = (1 << AT91C_PERIPHERAL_ID_PIOA); /* Need PIO too */ *AT91C_PMC_PCER = (1 << peripheral_id); /* Grab the pins we need */ *AT91C_PIOA_PDR = pinmask; *AT91C_PIOA_ASR = pinmask; up->US_CR = 0x5AC; // Disable up->US_MR = mode; up->US_IDR = 0xFFFFFFFF; up->US_BRGR = uart_calc_divisor(baudRate); // rw Baud rate generator up->US_RTOR = 0; // rw Receiver timeout up->US_TTGR = 0; // rw Transmitter time guard up->US_RPR = 0; // rw Receiver pointer up->US_RCR = 0; // rw Receiver counter up->US_TPR = 0; // rw Transmitter pointer up->US_TCR = 0; // rw Transmitter counter // Set up UART interrupt aic_mask_off(peripheral_id); aic_set_vector(peripheral_id, AIC_INT_LEVEL_NORMAL, isr); aic_mask_on(peripheral_id); // Finally enable the UART up->US_CR = 0x50; // enable tx and rx dummy = up->US_RHR; // dummy read. up->US_IER = 1; //Enable rx and tx interrupts. This should cause a bogus tx int if (i_state) interrupts_enable(); return 1; }