void
lcaattach(device_t parent, device_t self, void *aux)
{
struct lca_softc *sc = device_private(self);
struct lca_config *lcp;
struct pcibus_attach_args pba;
/* note that we've attached the chipset; can't have 2 LCAs. */
/* Um, not sure about this. XXX JH */
lcafound = 1;
sc->sc_dev = self;
/*
* set up the chipset's info; done once at console init time
* (maybe), but we must do it twice to take care of things
* that need to use memory allocation.
*/
lcp = sc->sc_lcp = &lca_configuration;
lca_init(lcp, 1);
/* XXX print chipset information */
aprint_normal("\n");
lca_dma_init(lcp);
switch (cputype) {
#ifdef DEC_AXPPCI_33
case ST_DEC_AXPPCI_33:
pci_axppci_33_pickintr(lcp);
break;
#endif
#ifdef DEC_ALPHABOOK1
case ST_ALPHABOOK1:
pci_alphabook1_pickintr(lcp);
break;
#endif
#ifdef DEC_EB66
case ST_EB66:
pci_eb66_pickintr(lcp);
break;
#endif
default:
panic("lcaattach: shouldn't be here, really...");
}
pba.pba_iot = &lcp->lc_iot;
pba.pba_memt = &lcp->lc_memt;
pba.pba_dmat =
alphabus_dma_get_tag(&lcp->lc_dmat_direct, ALPHA_BUS_PCI);
pba.pba_dmat64 = NULL;
pba.pba_pc = &lcp->lc_pc;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY |
PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
void
irongate_attach(struct device *parent, struct device *self, void *aux)
{
struct irongate_softc *sc = (void *) self;
struct irongate_config *icp;
struct pcibus_attach_args pba;
/* Note that we've attached the chipset; can't have 2 Irongates. */
irongate_found = 1;
/*
* Set up the chipset's info; done once at console init time
* (maybe), but we must do it here as well to take care of things
* that need to use memory allocation.
*/
icp = sc->sc_icp = &irongate_configuration;
irongate_init(icp, 1);
printf(": AMD 751 Core Logic + AGP Chipset, rev. %d\n", icp->ic_rev);
irongate_dma_init(icp);
/*
* Do PCI memory initialization that needs to be deferred until
* malloc is safe.
*/
irongate_bus_mem_init2(icp->ic_memt, icp);
switch (cputype) {
#ifdef API_UP1000
case ST_API_NAUTILUS:
pci_up1000_pickintr(icp);
break;
#endif
default:
panic("irongate_attach: shouldn't be here, really...");
}
pba.pba_busname = "pci";
pba.pba_iot = icp->ic_iot;
pba.pba_memt = icp->ic_memt;
pba.pba_dmat =
alphabus_dma_get_tag(&icp->ic_dmat_pci, ALPHA_BUS_PCI);
pba.pba_pc = &icp->ic_pc;
pba.pba_bus = 0;
#ifdef notyet
pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
#endif
(void) config_found(self, &pba, irongate_print);
}
void
ciaattach(device_t parent, device_t self, void *aux)
{
struct cia_softc *sc = device_private(self);
struct cia_config *ccp;
struct pcibus_attach_args pba;
char bits[64];
const char *name;
int pass;
/* note that we've attached the chipset; can't have 2 CIAs. */
ciafound = 1;
sc->sc_dev = self;
/*
* set up the chipset's info; done once at console init time
* (maybe), but we must do it here as well to take care of things
* that need to use memory allocation.
*/
ccp = sc->sc_ccp = &cia_configuration;
cia_init(ccp, 1);
if (ccp->cc_flags & CCF_ISPYXIS) {
name = "Pyxis";
pass = ccp->cc_rev;
} else {
name = "ALCOR/ALCOR2";
pass = ccp->cc_rev + 1;
}
aprint_normal(": DECchip 2117x Core Logic Chipset (%s), pass %d\n",
name, pass);
if (ccp->cc_cnfg) {
snprintb(bits, sizeof(bits), CIA_CSR_CNFG_BITS, ccp->cc_cnfg);
aprint_normal_dev(self, "extended capabilities: %s\n", bits);
}
switch (ccp->cc_flags & (CCF_PCI_USE_BWX|CCF_BUS_USE_BWX)) {
case CCF_PCI_USE_BWX|CCF_BUS_USE_BWX:
name = "PCI config and bus";
break;
case CCF_PCI_USE_BWX:
name = "PCI config";
break;
case CCF_BUS_USE_BWX:
name = "bus";
break;
default:
name = NULL;
break;
}
if (name != NULL)
aprint_normal_dev(self, "using BWX for %s access\n", name);
#ifdef DEC_550
if (cputype == ST_DEC_550 &&
(hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
/*
* Miata 1 systems have a bug: DMA cannot cross
* an 8k boundary! Make sure PCI read prefetching
* is disabled on these chips. Note that secondary
* PCI busses don't have this problem, because of
* the way PPBs handle PCI read requests.
*
* In the 21174 Technical Reference Manual, this is
* actually documented as "Pyxis Pass 1", but apparently
* there are chips that report themselves as "Pass 1"
* which do not have the bug! Miatas with the Cypress
* PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not
* have the bug, so we use this check.
*
* NOTE: This bug is actually worked around in cia_dma.c,
* when direct-mapped DMA maps are created.
*
* XXX WE NEED TO THINK ABOUT HOW TO HANDLE THIS FOR
* XXX SGMAP DMA MAPPINGS!
*/
uint32_t ctrl;
/* XXX no bets... */
aprint_error_dev(self,
"WARNING: Pyxis pass 1 DMA bug; no bets...\n");
ccp->cc_flags |= CCF_PYXISBUG;
alpha_mb();
ctrl = REGVAL(CIA_CSR_CTRL);
ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE);
REGVAL(CIA_CSR_CTRL) = ctrl;
alpha_mb();
}
#endif /* DEC_550 */
cia_dma_init(ccp);
switch (cputype) {
#ifdef DEC_KN20AA
case ST_DEC_KN20AA:
pci_kn20aa_pickintr(ccp);
break;
#endif
#ifdef DEC_EB164
case ST_EB164:
pci_eb164_pickintr(ccp);
break;
#endif
#ifdef DEC_550
case ST_DEC_550:
pci_550_pickintr(ccp);
break;
#endif
#ifdef DEC_1000A
case ST_DEC_1000A:
pci_1000a_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt,
&ccp->cc_pc);
break;
#endif
#ifdef DEC_1000
case ST_DEC_1000:
pci_1000_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt,
&ccp->cc_pc);
break;
#endif
default:
panic("ciaattach: shouldn't be here, really...");
}
pba.pba_iot = &ccp->cc_iot;
pba.pba_memt = &ccp->cc_memt;
pba.pba_dmat =
alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI);
pba.pba_dmat64 = NULL;
pba.pba_pc = &ccp->cc_pc;
pba.pba_bus = 0;
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
if ((ccp->cc_flags & CCF_PYXISBUG) == 0)
pba.pba_flags |= PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY |
PCI_FLAGS_MWI_OKAY;
config_found_ia(self, "pcibus", &pba, pcibusprint);
}
