uint8_t init_i2c(uint32_t i2c_dev){
void *virtual_base;
volatile uint32_t *i2c_ic_con = NULL;
volatile uint32_t *i2c_en = NULL;
int fd;
uint32_t daten_register;
//Oeffnen der Datei des Speichers mit Fehlerabrage
if( ( fd = open( "/dev/mem", ( O_RDWR | O_SYNC ) ) ) == -1 ) {
printf( "ERROR: could not open \"/dev/mem\"...\n" );
return 1;
}
//Erstellen einer Virtuellen Adresse
virtual_base = mmap( NULL, HW_REGS_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd, HW_REGS_BASE );
//Fehlerabrage der Virtuellen Adresse
if( virtual_base == MAP_FAILED ) {
printf( "ERROR: mmap() failed...\n" );
close( fd );
return 2;
}
//Erstellen einen Pointers auf das ic_con Register im Speicher
i2c_ic_con = virtual_base + ( (uint32_t)( i2c_dev + ic_con ) & (uint32_t)( HW_REGS_MASK ) );
//Erstellen einen Pointers auf das ic_enable Register im Speicher
i2c_en = virtual_base + ( (uint32_t)( i2c_dev + ic_enable ) & (uint32_t)( HW_REGS_MASK ) );
//Auschalten des I2C Moduls
alt_clrbits_word(i2c_en, 0x1);
//Auf 100kHz stellen
alt_write_word(i2c_ic_con, ( (alt_read_word(i2c_ic_con) & 0xFFFFFFF9) | 0x00000002) );
//Einschalten des I2C Moduls
alt_setbits_word(i2c_en, 0x1);
//Lesen des Registers
daten_register = alt_read_word(i2c_ic_con);
//Pruefen des Registerinhalts auf 0x73 oder 0x63
if(daten_register != 0x73){
if( daten_register != 0x63){
close( fd );
return 3;
}
}
//Memorryunmapping aufheben mti Fehlerabfrage
if( munmap( virtual_base, HW_REGS_SPAN ) != 0 ) {
printf( "ERROR: munmap() failed...\n" );
close( fd );
return( 4 );
}
//Datei schliesen
close( fd );
return 0;
}
// Receive single character
int mp_hal_stdin_rx_chr(void) {
// Wait until data ready
while (1 != ALT_UART_LSR_DR_GET(alt_read_word(ALT_UART0_LSR_ADDR))) { }
// Read character from THR
return alt_read_word(ALT_UART0_RBR_THR_DLL_ADDR);
}
// Return the L2 cache address filtering registers configuration settings in the
// user provided start and end address range out parameters.
ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,
uint32_t* addr_filt_end)
{
if (addr_filt_start == NULL || addr_filt_end == NULL)
{
return ALT_E_BAD_ARG;
}
uint32_t addr_filt_start_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_START_ADDR);
uint32_t addr_filt_end_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR);
*addr_filt_start = (addr_filt_start_reg & L2_CACHE_ADDR_FILTERING_START_ADDR_MASK);
*addr_filt_end = (addr_filt_end_reg & L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
return ALT_E_SUCCESS;
}
static int reg_read(uint32_t addr, uint32_t* data, uint32_t bytes_to_read) {
int fd, i;
void* virtual_base;
// round up the nearest PAGE_SIZE
uint32_t span = bytes_to_read / PAGE_SIZE;
if (span < bytes_to_read) span += PAGE_SIZE;
if( ( fd = open( MEM_DEV, O_RDONLY | O_SYNC ) ) < 0 ) {
PRINT(ERROR, "%s(), opening, %s\n", __func__, strerror(errno));
return RETURN_ERROR_COMM_MMAP;
}
virtual_base = mmap( NULL, span, PROT_READ, MAP_SHARED, fd, addr & ~(span-1) );
if( virtual_base == MAP_FAILED ) {
PRINT(ERROR, "%s(), mmap, %s\n", __func__, strerror(errno));
close( fd );
return RETURN_ERROR_COMM_MMAP;
}
// Does the actual reading
for (i = 0; i < bytes_to_read; i++) {
data[i] = alt_read_word(virtual_base + ((addr + i) & (span - 1)));
}
if( munmap( virtual_base, span ) != 0 ) {
PRINT(ERROR, "%s(), close, %s\n", __func__, strerror(errno));
close(fd);
return RETURN_ERROR_COMM_MMAP;
}
close(fd);
return RETURN_SUCCESS;
}
static bool altera_cyclone_v_uart_probe(
rtems_termios_device_context *base,
uint32_t uart_set_mask
)
{
ns16550_context *ctx = (ns16550_context *) base;
bool ret = true;
uint32_t ucr;
ALT_STATUS_CODE sc;
void* location = (void *) ctx->port;
/* The ALT_CLK_L4_SP is required for all SoCFPGA UARTs.
* Check that it's enabled. */
if ( alt_clk_is_enabled(ALT_CLK_L4_SP) != ALT_E_TRUE ) {
ret = false;
}
if ( ret ) {
sc = alt_clk_freq_get(ALT_CLK_L4_SP, &ctx->clock);
if ( sc != ALT_E_SUCCESS ) {
ret = false;
}
}
if ( ret ) {
// Bring UART out of reset.
alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, uart_set_mask);
// Verify the UCR (UART Component Version)
ucr = alt_read_word( ALT_UART_UCV_ADDR( location ) );
if ( ucr != ALT_UART_UCV_UART_COMPONENT_VER_RESET ) {
ret = false;
}
}
if ( ret ) {
// Write SRR::UR (Shadow Reset Register :: UART Reset)
alt_write_word( ALT_UART_SRR_ADDR( location ), ALT_UART_SRR_UR_SET_MSK );
// Read the MSR to work around case:119085.
(void)alt_read_word( ALT_UART_MSR_ADDR( location ) );
ret = ns16550_probe( base );
}
return ret;
}
ALT_STATUS_CODE alt_nand_flash_ecc_status_get(ALT_NAND_FLASH_ECC_STATUS_t *ecc_status)
{
ALT_NAND_ECC_raw_t * ecc = (ALT_NAND_ECC_raw_t *)(nand->ecc);
uint32_t status;
status = alt_read_word(&ecc->ECCCorInfo_b01);
ecc_status->corrected_errors[0] = (status & ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_LSB;
ecc_status->corrected_errors[1] = (status & ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_LSB;
ecc_status->uncorrected_error[0] = (status & ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_LSB;
ecc_status->uncorrected_error[1] = (status & ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_LSB;
status = alt_read_word(&ecc->ECCCorInfo_b23);
ecc_status->corrected_errors[2] = (status & ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_LSB;
ecc_status->corrected_errors[3] = (status & ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_LSB;
ecc_status->uncorrected_error[2] = (status & ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_LSB;
ecc_status->uncorrected_error[3] = (status & ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET_MSK) >> ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_LSB;
return ALT_E_SUCCESS;
}
static ALT_STATUS_CODE alt_ocram_ecc_start(void * block, size_t size)
{
const uint32_t ocram_size = ((uint32_t)ALT_OCRAM_UB_ADDR - (uint32_t)ALT_OCRAM_LB_ADDR) + 1;
dprintf("DEBUG[ECC][OCRAM]: OCRAM Size = 0x%lx.\n", ocram_size);
// Verify buffer is large enough to contain the entire contents of OCRAM.
if (size < ocram_size)
{
return ALT_E_ERROR;
}
// Verify buffer is word aligned.
if ((uintptr_t)block & (sizeof(uint32_t) - 1))
{
return ALT_E_ERROR;
}
// Read the contents of OCRAM into the provided buffer
uint32_t * block_iter = block;
uint32_t * ocram_iter = ALT_OCRAM_ADDR;
uint32_t size_counter = ocram_size;
while (size_counter)
{
*block_iter = alt_read_word(ocram_iter);
++block_iter;
++ocram_iter;
size_counter -= sizeof(*ocram_iter);
}
// Enable ECC
alt_setbits_word(ALT_SYSMGR_ECC_OCRAM_ADDR, ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK);
// Write back contents of OCRAM from buffer to OCRAM
block_iter = block;
ocram_iter = ALT_OCRAM_ADDR;
size_counter = ocram_size;
while (size_counter)
{
alt_write_word(ocram_iter, *block_iter);
++block_iter;
++ocram_iter;
size_counter -= sizeof(*ocram_iter);
}
// Clear any pending spurious interrupts
alt_write_word(ALT_SYSMGR_ECC_OCRAM_ADDR,
ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK
| ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK
| ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK);
return ALT_E_SUCCESS;
}
// Send string of given length
void mp_hal_stdout_tx_strn(const char *str, mp_uint_t len) {
for (int i = 0; i < len; i++) {
// Wait until THR is empty
while (1 != ALT_UART_LSR_THRE_GET(alt_read_word(ALT_UART0_LSR_ADDR))) { }
// Write character to THR
alt_write_word(ALT_UART0_RBR_THR_DLL_ADDR, str[i]);
}
}
ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id)
{
if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
uint32_t awuser, page;
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
awuser = ALT_ACPIDMAP_VID2WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
page = ALT_ACPIDMAP_VID2WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
awuser = ALT_ACPIDMAP_VID3WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
page = ALT_ACPIDMAP_VID3WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
awuser = ALT_ACPIDMAP_VID4WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
page = ALT_ACPIDMAP_VID4WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
awuser = ALT_ACPIDMAP_VID5WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
page = ALT_ACPIDMAP_VID5WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
awuser = ALT_ACPIDMAP_VID6WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
page = ALT_ACPIDMAP_VID6WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
break;
default:
return ALT_E_BAD_ARG;
}
alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,
ALT_ACPIDMAP_DYNWR_PAGE_SET(page)
| ALT_ACPIDMAP_DYNWR_USER_SET(awuser));
return ALT_E_SUCCESS;
}
int _write(int file, char * ptr, unsigned len, int flag )
{
/* Fails if not STDOUT */
if(file != STDOUT_FILENO)
{
return -1;
}
/* Print each character to UART */
for(int i=0; i<len; i++)
{
/* Wait until THR is empty*/
while(1 != ALT_UART_LSR_THRE_GET(alt_read_word(ALT_UART0_LSR_ADDR)))
{
}
/* Write character to THR */
alt_write_word(ALT_UART0_RBR_THR_DLL_ADDR, ptr[i]);
}
/* All printed fine */
return len;
}
ALT_STATUS_CODE alt_ecc_is_enabled(const ALT_ECC_RAM_ENUM_t ram_block)
{
void * ecc_addr;
uint32_t ecc_bits;
switch (ram_block)
{
case ALT_ECC_RAM_L2_DATA:
ecc_addr = ALT_SYSMGR_ECC_L2_ADDR;
ecc_bits = ALT_SYSMGR_ECC_L2_EN_SET_MSK;
break;
case ALT_ECC_RAM_OCRAM:
ecc_addr = ALT_SYSMGR_ECC_OCRAM_ADDR;
ecc_bits = ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK;
break;
case ALT_ECC_RAM_USB0:
ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB0_EN_SET_MSK;
break;
case ALT_ECC_RAM_USB1:
ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB1_EN_SET_MSK;
break;
case ALT_ECC_RAM_EMAC0:
ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK;
break;
case ALT_ECC_RAM_EMAC1:
ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK;
break;
case ALT_ECC_RAM_DMA:
ecc_addr = ALT_SYSMGR_ECC_DMA_ADDR;
ecc_bits = ALT_SYSMGR_ECC_DMA_EN_SET_MSK;
break;
case ALT_ECC_RAM_CAN0:
ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN0_EN_SET_MSK;
break;
case ALT_ECC_RAM_CAN1:
ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN1_EN_SET_MSK;
break;
case ALT_ECC_RAM_NAND:
ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR;
ecc_bits = ALT_SYSMGR_ECC_NAND_EN_SET_MSK;
break;
case ALT_ECC_RAM_QSPI:
ecc_addr = ALT_SYSMGR_ECC_QSPI_ADDR;
ecc_bits = ALT_SYSMGR_ECC_QSPI_EN_SET_MSK;
break;
case ALT_ECC_RAM_SDMMC:
ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR;
ecc_bits = ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK;
break;
default:
return ALT_E_ERROR;
}
if (alt_read_word(ecc_addr) & ecc_bits)
{
return ALT_E_TRUE;
}
else
{
return ALT_E_FALSE;
}
}
//=======================================================================================
// EJECUCIÓN FILTRO FIR
//=======================================================================================
int main(int argc, char *argv[])
{
if (argc > 1)
{
}
else
{
printf("The command had no other arguments.\n");
return 0;
}
//<><><><><><><><><><><><><><><><><>//
// SYSTEM INITIALIZING //
//<><><><><><><><><><><><><><><><><>//
init_system();
//<><><><><><><><><><><><><><><><><>//
// SIGNALS DECLARATION //
//<><><><><><><><><><><><><><><><><>//
FIR_filter filtro,filtro2,filtro3;
SIGNAL signal1;
SIGNAL signal1_output;
SIGNAL signal2_output;
SIGNAL signal3_output;
sscanf (argv[1],"%d",&filtro.F1);
sscanf (argv[2],"%d",&filtro.F2);
sscanf (argv[3],"%d",&filtro.order);
sscanf (argv[4],"%d",&filtro.FS);
sscanf (argv[5],"%d",&filtro.window_type);
sscanf (argv[6],"%d",&filtro.filter_type);
sscanf (argv[7],"%d",&filtro.sw_hw);
// filtro.F1=12071;
// filtro.F2=12171;
// filtro.order=200;
// filtro.FS=44100;
// filtro.window_type=BLACKMAN_HARRIS;
// filtro.filter_type=BS_FILTER;
//<><><><><><><><><><><><><><><><><>//
// FILTER COEFFICIENTS CALCULATION //
//<><><><><><><><><><><><><><><><><>//
calc_FIR_coefs(&filtro);
// calc_FIR_coefs(&filtro2);
// calc_FIR_coefs(&filtro3);
//<><><><><><><><><><><><><><><><><>//
// LOAD FILE //
//<><><><><><><><><><><><><><><><><>//
load_signal(&signal1,argv[8]);
//<><><><><><><><><><><><><><><><><>//
// SIGNAL REPLICATION //
//<><><><><><><><><><><><><><><><><>//
signal1_output.lenght=signal1.lenght;
// signal2_output.lenght=signal1.lenght;
// signal3_output.lenght=signal1.lenght;
signal1_output.signal=(int*) malloc (sizeof(int)*signal1.lenght);
// signal2_output.signal=(int*) malloc (sizeof(int)*signal1.lenght);
// signal3_output.signal=(int*) malloc (sizeof(int)*signal1.lenght);
//<><><><><><><><><><><><><><><><><>//
// START TIMER //
//<><><><><><><><><><><><><><><><><>//
alt_write_word(h2p_start_timer_addr, 1 ); //0:ligh, 1:unlight
//<><><><><><><><><><><><><><><><><>//
// APPLY FILTER & NORMALIZE SIGNAL //
//<><><><><><><><><><><><><><><><><>//
normalize_signal( &signal1, 128);
apply_FIR_whole_signal(&filtro, &signal1, &signal1_output);
normalize_signal( &signal1_output, 128);
// apply_FIR_whole_signal(&filtro2, &signal1_output, &signal2_output);
// normalize_signal( &signal2_output, 128);
// apply_FIR_whole_signal(&filtro3, &signal2_output, &signal3_output);
// normalize_signal( &signal3_output, 128);
//<><><><><><><><><><><><><><><><><>//
// GET TICK <TIMER> //
//<><><><><><><><><><><><><><><><><>//
int time_cont;
time_cont = alt_read_word(p2h_get_tick_addr);
printf("valor del timer: %d\n",time_cont);
//<><><><><><><><><><><><><><><><><>//
// TIMER SHUTDOWN //
//<><><><><><><><><><><><><><><><><>//
alt_write_word(h2p_start_timer_addr, 0 );
save_signal( &signal1_output, argv[9]);
// save_signal( &signal2_output, "filtrito2.bin");
// save_signal( &signal3_output, "filtrito3.bin");
printf("Finalizando Ejecucion.\n");
return 0;
}
ALT_STATUS_CODE alt_ecc_status_clear(const ALT_ECC_RAM_ENUM_t ram_block,
const uint32_t ecc_mask)
{
void * ecc_addr;
uint32_t ecc_bits = 0;
switch (ram_block)
{
// case ALT_ECC_RAM_L2_DATA:
case ALT_ECC_RAM_OCRAM:
ecc_addr = ALT_SYSMGR_ECC_OCRAM_ADDR;
if (ecc_mask & ALT_ECC_ERROR_OCRAM_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_OCRAM_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_USB0:
ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR;
if (ecc_mask & ALT_ECC_ERROR_USB0_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_USB0_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_USB0_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_USB0_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_USB1:
ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR;
if (ecc_mask & ALT_ECC_ERROR_USB1_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_USB1_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_USB1_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_USB1_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_EMAC0:
ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR;
if (ecc_mask & ALT_ECC_ERROR_EMAC0_TX_FIFO_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_EMAC0_TX_FIFO_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_EMAC0_RX_FIFO_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_EMAC0_RX_FIFO_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK;
}
break;
case ALT_ECC_RAM_EMAC1:
ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR;
if (ecc_mask & ALT_ECC_ERROR_EMAC1_TX_FIFO_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_EMAC1_TX_FIFO_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_EMAC1_RX_FIFO_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_EMAC1_RX_FIFO_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK;
}
break;
case ALT_ECC_RAM_DMA:
ecc_addr = ALT_SYSMGR_ECC_DMA_ADDR;
if (ecc_mask & ALT_ECC_ERROR_DMA_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_DMA_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_DMA_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_DMA_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_CAN0:
ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR;
if (ecc_mask & ALT_ECC_ERROR_CAN0_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_CAN0_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_CAN1:
ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR;
if (ecc_mask & ALT_ECC_ERROR_CAN1_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_CAN1_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_NAND:
ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR;
if (ecc_mask & ALT_ECC_ERROR_NAND_BUFFER_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_NAND_BUFFER_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_NAND_WR_FIFO_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_NAND_WR_FIFO_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_NAND_RD_FIFO_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_NAND_RD_FIFO_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK;
}
break;
case ALT_ECC_RAM_QSPI:
ecc_addr = ALT_SYSMGR_ECC_QSPI_ADDR;
if (ecc_mask & ALT_ECC_ERROR_QSPI_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_QSPI_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK;
}
break;
case ALT_ECC_RAM_SDMMC:
ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR;
if (ecc_mask & ALT_ECC_ERROR_SDMMC_PORT_A_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_SDMMC_PORT_A_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_SDMMC_PORT_B_SERR)
{
ecc_bits |= ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK;
}
if (ecc_mask & ALT_ECC_ERROR_SDMMC_PORT_B_DERR)
{
ecc_bits |= ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK;
}
break;
default:
return ALT_E_ERROR;
}
// Bit 1 is always ECC enable.
// Be sure not to clear other conditions that may be active but not requested to be cleared.
alt_write_word(ecc_addr, (alt_read_word(ecc_addr) & (1 << 0)) | ecc_bits);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_fpga_interface_is_enabled(ALT_FPGA_INTERFACE_t intfc)
{
switch (intfc)
{
case ALT_FPGA_INTERFACE_GLOBAL:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_GBL_ADDR) &
ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_RESET_REQ:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_JTAG_ENABLE:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_CONFIG_IO:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_BSCAN:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_TRACE:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_DBG_APB:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
(1 << 5)) != 0) ? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_STM:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_CTI:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_INDIV_ADDR) &
ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_EMAC0:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) &
ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_EMAC1:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) &
ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_SPIM0:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) &
(1 << 0)) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_SPIM1:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) &
(1 << 1)) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_NAND:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) &
(1 << 4)) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
case ALT_FPGA_INTERFACE_SDMMC:
return ((alt_read_word(ALT_SYSMGR_FPGAINTF_MODULE_ADDR) &
(1 << 5)) != 0)
? ALT_E_TRUE : ALT_E_FALSE;
default:
return ALT_E_BAD_ARG;
}
}
/***************************************************************************//**
* @brief dac_read
*******************************************************************************/
void dac_read(uint32_t regAddr, uint32_t *data)
{
*data = alt_read_word(CF_AD9361_TX_BASEADDR + regAddr);
}
ALT_STATUS_CODE alt_ecc_derr_inject(const ALT_ECC_RAM_ENUM_t ram_block)
{
void * ecc_addr;
uint32_t ecc_bits;
switch (ram_block)
{
case ALT_ECC_RAM_L2_DATA:
ecc_addr = ALT_SYSMGR_ECC_L2_ADDR;
ecc_bits = ALT_SYSMGR_ECC_L2_INJD_SET_MSK;
break;
case ALT_ECC_RAM_OCRAM:
ecc_addr = ALT_SYSMGR_ECC_OCRAM_ADDR;
ecc_bits = ALT_SYSMGR_ECC_OCRAM_INJD_SET_MSK;
break;
case ALT_ECC_RAM_USB0:
ecc_addr = ALT_SYSMGR_ECC_USB0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB0_INJD_SET_MSK;
break;
case ALT_ECC_RAM_USB1:
ecc_addr = ALT_SYSMGR_ECC_USB1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_USB1_INJD_SET_MSK;
break;
case ALT_ECC_RAM_EMAC0:
ecc_addr = ALT_SYSMGR_ECC_EMAC0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET_MSK
| ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET_MSK;
break;
case ALT_ECC_RAM_EMAC1:
ecc_addr = ALT_SYSMGR_ECC_EMAC1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET_MSK
| ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET_MSK;
break;
case ALT_ECC_RAM_DMA:
ecc_addr = ALT_SYSMGR_ECC_DMA_ADDR;
ecc_bits = ALT_SYSMGR_ECC_DMA_INJD_SET_MSK;
break;
case ALT_ECC_RAM_CAN0:
ecc_addr = ALT_SYSMGR_ECC_CAN0_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN0_INJD_SET_MSK;
break;
case ALT_ECC_RAM_CAN1:
ecc_addr = ALT_SYSMGR_ECC_CAN1_ADDR;
ecc_bits = ALT_SYSMGR_ECC_CAN1_INJD_SET_MSK;
break;
case ALT_ECC_RAM_NAND:
ecc_addr = ALT_SYSMGR_ECC_NAND_ADDR;
ecc_bits = ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET_MSK
| ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET_MSK
| ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET_MSK;
break;
case ALT_ECC_RAM_QSPI:
ecc_addr = ALT_SYSMGR_ECC_QSPI_ADDR;
ecc_bits = ALT_SYSMGR_ECC_QSPI_INJD_SET_MSK;
break;
case ALT_ECC_RAM_SDMMC:
ecc_addr = ALT_SYSMGR_ECC_SDMMC_ADDR;
ecc_bits = ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET_MSK
| ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET_MSK;
break;
default:
return ALT_E_ERROR;
}
uint32_t reg = alt_read_word(ecc_addr);
alt_write_word(ecc_addr, reg | ecc_bits);
alt_write_word(ecc_addr, reg);
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id,
bool * fixed,
uint32_t * input_id,
ALT_ACP_ID_MAP_PAGE_t * page,
uint32_t * awuser)
{
if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
{
return ALT_E_BAD_ARG;
}
switch (output_id)
{
case ALT_ACP_ID_OUT_FIXED_ID_2:
*awuser = ALT_ACPIDMAP_VID2WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID2WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID2WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_3:
*awuser = ALT_ACPIDMAP_VID3WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID3WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID3WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_4:
*awuser = ALT_ACPIDMAP_VID4WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID4WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID4WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_5:
*awuser = ALT_ACPIDMAP_VID5WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID5WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID5WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_6:
*awuser = ALT_ACPIDMAP_VID6WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
*input_id = ALT_ACPIDMAP_VID6WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
*fixed = ALT_ACPIDMAP_VID6WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
break;
case ALT_ACP_ID_OUT_DYNAM_ID_7:
*awuser = ALT_ACPIDMAP_DYNWR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
*page = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNWR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
break;
default:
return ALT_E_BAD_ARG;
}
return ALT_E_SUCCESS;
}
ALT_STATUS_CODE alt_nand_flash_init(const bool load_block0_page0,
const bool page_size_512,
alt_nand_flash_custom_init_t custom_init,
void *user_arg)
{
ALT_NAND_CFG_raw_t * cfg = (ALT_NAND_CFG_raw_t *)(nand->cfg);
ALT_NAND_PARAM_raw_t * param = (ALT_NAND_PARAM_raw_t *)(nand->param);
ALT_STATUS_CODE ret = ALT_E_SUCCESS;
uint32_t x;
alt_setbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_NAND_SET_MSK);
alt_nand_set_sysmgr_bootstrap_value( ALT_NAND_BOOTSTRAP_INHIBIT_INIT_DISABLE,
load_block0_page0,
page_size_512,
ALT_NAND_BOOTSTRAP_TWO_ROW_ADDR_CYCLES_DISABLE
);
alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_NAND_SET_MSK);
g_nand_interrup_status_register_poll_counter_limit = (uint32_t)(-1);
ret = (*custom_init)(user_arg);
if (ret == ALT_E_RESERVED) // no custom initialization being done
{
alt_nand_reset_bank(0);
}
// Read flash device characterization
flash->manufacturer_id = alt_read_word(¶m->manufacturer_id);
flash->device_id = alt_read_word(¶m->device_id);
flash->device_param_0 = alt_read_word(¶m->device_param_0);
flash->device_param_1 = alt_read_word(¶m->device_param_1);
flash->device_param_2 = alt_read_word(¶m->device_param_2);
flash->page_size = alt_read_word(&cfg->device_main_area_size);
flash->spare_size = alt_read_word(&cfg->device_spare_area_size);
flash->revision = alt_read_word(¶m->revision);
flash->onfi_device_features = alt_read_word(¶m->onfi_device_features);
flash->onfi_optional_commands = alt_read_word(¶m->onfi_optional_commands);
flash->onfi_timing_mode = alt_read_word(¶m->onfi_timing_mode);
flash->onfi_pgm_cache_timing_mode = alt_read_word(¶m->onfi_pgm_cache_timing_mode);
flash->onfi_compliant = alt_read_word(¶m->onfi_device_no_of_luns) >> 8;
flash->onfi_device_no_of_luns = alt_read_word(¶m->onfi_device_no_of_luns) & 0xff;
x = alt_read_word(¶m->onfi_device_no_of_blocks_per_lun_l);
flash->onfi_device_no_of_blocks_per_lun = (alt_read_word(¶m->onfi_device_no_of_blocks_per_lun_u) << 16) + x;
flash->features = alt_read_word(¶m->features);
x = alt_read_word(&cfg->number_of_planes);
switch (x)
{
case 0:
flash->number_of_planes = 1;
break;
case 1:
flash->number_of_planes = 2;
break;
case 3:
flash->number_of_planes = 4;
break;
case 7:
flash->number_of_planes = 4;
break;
default:
flash->number_of_planes = 1;
break;
}
flash->pages_per_block = alt_read_word(&cfg->pages_per_block);
// Device Width register content should automatically update SystemManager:NandGrp:BootStrap:page512 or page512x16 bit
flash->device_width = alt_read_word(&cfg->device_width);
// Set the skip bytes and then read back the result.
alt_write_word(&cfg->spare_area_skip_bytes, flash->spare_area_skip_bytes);
flash->spare_area_skip_bytes = alt_read_word(&cfg->spare_area_skip_bytes);
flash->block_size = flash->pages_per_block * flash->page_size;
flash->first_block_of_next_plane = alt_read_word(&cfg->first_block_of_next_plane);
// Set flash config based on read config
flash->page_size_32 = flash->page_size / sizeof(uint32_t);
flash->page_shift = ffs32(flash->page_size);
flash->block_shift = ffs32(flash->pages_per_block);
alt_nand_rb_pin_mode_clear(ALT_NAND_CFG_RB_PIN_END_BANK0_SET_MSK);
alt_nand_flash_ecc_disable();
alt_write_word(&cfg->first_block_of_next_plane,alt_nand_number_blocks_of_plane_get());
flash->first_block_of_next_plane = alt_read_word(&cfg->first_block_of_next_plane);
return ALT_E_SUCCESS;
}
// Remap the MPU address space view of address 0 to access the SDRAM controller.
// This is done by setting the L2 cache address filtering register start address
// to 0 and leaving the address filtering address end address value
// unmodified. This causes all physical addresses in the range
// address_filter_start <= physical_address < address_filter_end to be directed
// to the to the AXI Master Port M1 which is connected to the SDRAM
// controller. All other addresses are directed to AXI Master Port M0 which
// connect the MPU subsystem to the L3 interconnect.
//
// It is unnecessary to modify the MPU remap options in the L3 remap register
// because those options only affect addresses in the MPU subsystem address
// ranges that are now redirected to the SDRAM controller and never reach the L3
// interconnect anyway.
ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void)
{
uint32_t addr_filt_end = (alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR) &
L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
return alt_l2_addr_filter_cfg_set(0x0, addr_filt_end);
}
uint32_t alt_nand_int_status_get(void)
{
uint32_t bank = alt_nand_bank_get();
uint32_t reg = alt_nand_get_interrupt_status_register_addr(bank);
return alt_read_word(reg);
}
ALT_STATUS_CODE alt_ecc_status_get(const ALT_ECC_RAM_ENUM_t ram_block,
uint32_t *status)
{
uint32_t ecc_bits;
uint32_t ecc_mask = 0;
switch (ram_block)
{
// case ALT_ECC_RAM_L2_DATA:
case ALT_ECC_RAM_OCRAM:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_OCRAM_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_OCRAM_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_OCRAM_DERR;
}
break;
case ALT_ECC_RAM_USB0:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_USB0_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_USB0_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_USB0_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_USB0_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_USB0_DERR;
}
break;
case ALT_ECC_RAM_USB1:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_USB1_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_USB1_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_USB1_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_USB1_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_USB1_DERR;
}
break;
case ALT_ECC_RAM_EMAC0:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_EMAC0_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC0_TX_FIFO_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC0_TX_FIFO_DERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC0_RX_FIFO_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC0_RX_FIFO_DERR;
}
break;
case ALT_ECC_RAM_EMAC1:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_EMAC1_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC1_TX_FIFO_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC1_TX_FIFO_DERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC1_RX_FIFO_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_EMAC1_RX_FIFO_DERR;
}
break;
case ALT_ECC_RAM_DMA:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_DMA_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_DMA_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_DMA_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_DMA_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_DMA_DERR;
}
break;
case ALT_ECC_RAM_CAN0:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_CAN0_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_CAN0_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_CAN0_DERR;
}
break;
case ALT_ECC_RAM_CAN1:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_CAN1_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_CAN1_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_CAN1_DERR;
}
break;
case ALT_ECC_RAM_NAND:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_NAND_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_NAND_BUFFER_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_NAND_BUFFER_DERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_NAND_WR_FIFO_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_NAND_WR_FIFO_DERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_NAND_RD_FIFO_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_NAND_RD_FIFO_DERR;
}
break;
case ALT_ECC_RAM_QSPI:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_QSPI_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_QSPI_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_QSPI_DERR;
}
break;
case ALT_ECC_RAM_SDMMC:
ecc_bits = alt_read_word(ALT_SYSMGR_ECC_SDMMC_ADDR);
if (ecc_bits & ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_SDMMC_PORT_A_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_SDMMC_PORT_A_DERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_SDMMC_PORT_B_SERR;
}
if (ecc_bits & ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK)
{
ecc_mask |= ALT_ECC_ERROR_SDMMC_PORT_B_DERR;
}
break;
default:
return ALT_E_ERROR;
}
*status = ecc_mask;
return ALT_E_SUCCESS;
}
uint32_t alt_reset_event_get(void)
{
return alt_read_word(ALT_RSTMGR_STAT_ADDR);
}