s32 amhevc_loadmc_ex(const char*name, char *def) { if (HAS_HEVC_VDEC) return am_loadmc_ex(name, def, &amhevc_loadmc); else return 0; }
s32 amvdec2_loadmc_ex(const char*name,char *def) { if (HAS_VDEC2) { return am_loadmc_ex(name,def,&amvdec2_loadmc); } else { return 0; } }
s32 amhcodec_loadmc_ex(const char*name,char *def) { return am_loadmc_ex(name,def,&amhcodec_loadmc); }
static s32 amvdec_loadmc(const u32 *p) { ulong timeout; s32 ret = 0; #ifdef AMVDEC_USE_STATIC_MEMORY if (mc_addr == NULL) { #else { #endif mc_addr = kmalloc(MC_SIZE, GFP_KERNEL); } if (!mc_addr) return -ENOMEM; memcpy(mc_addr, p, MC_SIZE); mc_addr_map = dma_map_single(amports_get_dma_device(), mc_addr, MC_SIZE, DMA_TO_DEVICE); WRITE_VREG(MPSR, 0); WRITE_VREG(CPSR, 0); /* Read CBUS register for timing */ timeout = READ_VREG(MPSR); timeout = READ_VREG(MPSR); timeout = jiffies + HZ; WRITE_VREG(IMEM_DMA_ADR, mc_addr_map); WRITE_VREG(IMEM_DMA_COUNT, 0x1000); WRITE_VREG(IMEM_DMA_CTRL, (0x8000 | (7 << 16))); while (READ_VREG(IMEM_DMA_CTRL) & 0x8000) { if (time_before(jiffies, timeout)) schedule(); else { pr_err("vdec load mc error\n"); ret = -EBUSY; break; } } dma_unmap_single(amports_get_dma_device(), mc_addr_map, MC_SIZE, DMA_TO_DEVICE); #ifndef AMVDEC_USE_STATIC_MEMORY kfree(mc_addr); mc_addr = NULL; #endif return ret; } s32 amvdec_loadmc_ex(enum vformat_e type, const char *name, char *def) { return am_loadmc_ex(type, name, def, &amvdec_loadmc); } static s32 amvdec2_loadmc(const u32 *p) { if (has_vdec2()) { ulong timeout; s32 ret = 0; #ifdef AMVDEC_USE_STATIC_MEMORY if (mc_addr == NULL) { #else { #endif mc_addr = kmalloc(MC_SIZE, GFP_KERNEL); } if (!mc_addr) return -ENOMEM; memcpy(mc_addr, p, MC_SIZE); mc_addr_map = dma_map_single(amports_get_dma_device(), mc_addr, MC_SIZE, DMA_TO_DEVICE); WRITE_VREG(VDEC2_MPSR, 0); WRITE_VREG(VDEC2_CPSR, 0); /* Read CBUS register for timing */ timeout = READ_VREG(VDEC2_MPSR); timeout = READ_VREG(VDEC2_MPSR); timeout = jiffies + HZ; WRITE_VREG(VDEC2_IMEM_DMA_ADR, mc_addr_map); WRITE_VREG(VDEC2_IMEM_DMA_COUNT, 0x1000); WRITE_VREG(VDEC2_IMEM_DMA_CTRL, (0x8000 | (7 << 16))); while (READ_VREG(VDEC2_IMEM_DMA_CTRL) & 0x8000) { if (time_before(jiffies, timeout)) schedule(); else { pr_err("vdec2 load mc error\n"); ret = -EBUSY; break; } } dma_unmap_single(amports_get_dma_device(), mc_addr_map, MC_SIZE, DMA_TO_DEVICE); #ifndef AMVDEC_USE_STATIC_MEMORY kfree(mc_addr); mc_addr = NULL; #endif return ret; } else return 0; } s32 amvdec2_loadmc_ex(enum vformat_e type, const char *name, char *def) { if (has_vdec2()) return am_loadmc_ex(type, name, def, &amvdec2_loadmc); else return 0; } s32 amhcodec_loadmc(const u32 *p) { #ifdef AMVDEC_USE_STATIC_MEMORY if (mc_addr == NULL) { #else { #endif mc_addr = kmalloc(MC_SIZE, GFP_KERNEL); } if (!mc_addr) return -ENOMEM; memcpy(mc_addr, p, MC_SIZE); mc_addr_map = dma_map_single(amports_get_dma_device(), mc_addr, MC_SIZE, DMA_TO_DEVICE); WRITE_VREG(HCODEC_IMEM_DMA_ADR, mc_addr_map); WRITE_VREG(HCODEC_IMEM_DMA_COUNT, 0x100); WRITE_VREG(HCODEC_IMEM_DMA_CTRL, (0x8000 | (7 << 16))); while (READ_VREG(HCODEC_IMEM_DMA_CTRL) & 0x8000) udelay(1000); dma_unmap_single(amports_get_dma_device(), mc_addr_map, MC_SIZE, DMA_TO_DEVICE); #ifndef AMVDEC_USE_STATIC_MEMORY kfree(mc_addr); #endif return 0; } s32 amhcodec_loadmc_ex(enum vformat_e type, const char *name, char *def) { return am_loadmc_ex(type, name, def, &amhcodec_loadmc); } static s32 amhevc_loadmc(const u32 *p) { ulong timeout; s32 ret = 0; if (has_hevc_vdec()) { #ifdef AMVDEC_USE_STATIC_MEMORY if (mc_addr == NULL) { #else { #endif mc_addr = kmalloc(MC_SIZE, GFP_KERNEL); } if (!mc_addr) return -ENOMEM; memcpy(mc_addr, p, MC_SIZE); mc_addr_map = dma_map_single(amports_get_dma_device(), mc_addr, MC_SIZE, DMA_TO_DEVICE); WRITE_VREG(HEVC_MPSR, 0); WRITE_VREG(HEVC_CPSR, 0); /* Read CBUS register for timing */ timeout = READ_VREG(HEVC_MPSR); timeout = READ_VREG(HEVC_MPSR); timeout = jiffies + HZ; WRITE_VREG(HEVC_IMEM_DMA_ADR, mc_addr_map); WRITE_VREG(HEVC_IMEM_DMA_COUNT, 0x1000); WRITE_VREG(HEVC_IMEM_DMA_CTRL, (0x8000 | (7 << 16))); while (READ_VREG(HEVC_IMEM_DMA_CTRL) & 0x8000) { if (time_before(jiffies, timeout)) schedule(); else { pr_err("vdec2 load mc error\n"); ret = -EBUSY; break; } } dma_unmap_single(amports_get_dma_device(), mc_addr_map, MC_SIZE, DMA_TO_DEVICE); #ifndef AMVDEC_USE_STATIC_MEMORY kfree(mc_addr); mc_addr = NULL; #endif } return ret; } s32 amhevc_loadmc_ex(enum vformat_e type, const char *name, char *def) { if (has_hevc_vdec()) return am_loadmc_ex(type, name, def, &amhevc_loadmc); else return 0; } void amvdec_start(void) { #ifdef CONFIG_WAKELOCK amvdec_wake_lock(); #endif /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { READ_VREG(DOS_SW_RESET0); READ_VREG(DOS_SW_RESET0); READ_VREG(DOS_SW_RESET0); WRITE_VREG(DOS_SW_RESET0, (1 << 12) | (1 << 11)); WRITE_VREG(DOS_SW_RESET0, 0); READ_VREG(DOS_SW_RESET0); READ_VREG(DOS_SW_RESET0); READ_VREG(DOS_SW_RESET0); } else { /* #else */ /* additional cbus dummy register reading for timing control */ READ_MPEG_REG(RESET0_REGISTER); READ_MPEG_REG(RESET0_REGISTER); READ_MPEG_REG(RESET0_REGISTER); READ_MPEG_REG(RESET0_REGISTER); WRITE_MPEG_REG(RESET0_REGISTER, RESET_VCPU | RESET_CCPU); READ_MPEG_REG(RESET0_REGISTER); READ_MPEG_REG(RESET0_REGISTER); READ_MPEG_REG(RESET0_REGISTER); } /* #endif */ WRITE_VREG(MPSR, 0x0001); } void amvdec2_start(void) { if (has_vdec2()) { #ifdef CONFIG_WAKELOCK amvdec_wake_lock(); #endif READ_VREG(DOS_SW_RESET2); READ_VREG(DOS_SW_RESET2); READ_VREG(DOS_SW_RESET2); WRITE_VREG(DOS_SW_RESET2, (1 << 12) | (1 << 11)); WRITE_VREG(DOS_SW_RESET2, 0); READ_VREG(DOS_SW_RESET2); READ_VREG(DOS_SW_RESET2); READ_VREG(DOS_SW_RESET2); WRITE_VREG(VDEC2_MPSR, 0x0001); } } void amhcodec_start(void) { WRITE_VREG(HCODEC_MPSR, 0x0001); } void amhevc_start(void) { if (has_hevc_vdec()) { #ifdef CONFIG_WAKELOCK amvdec_wake_lock(); #endif READ_VREG(DOS_SW_RESET3); READ_VREG(DOS_SW_RESET3); READ_VREG(DOS_SW_RESET3); WRITE_VREG(DOS_SW_RESET3, (1 << 12) | (1 << 11)); WRITE_VREG(DOS_SW_RESET3, 0); READ_VREG(DOS_SW_RESET3); READ_VREG(DOS_SW_RESET3); READ_VREG(DOS_SW_RESET3); WRITE_VREG(HEVC_MPSR, 0x0001); } } void amvdec_stop(void) { ulong timeout = jiffies + HZ; WRITE_VREG(MPSR, 0); WRITE_VREG(CPSR, 0); while (READ_VREG(IMEM_DMA_CTRL) & 0x8000) { if (time_after(jiffies, timeout)) break; } /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { READ_VREG(DOS_SW_RESET0); READ_VREG(DOS_SW_RESET0); READ_VREG(DOS_SW_RESET0); WRITE_VREG(DOS_SW_RESET0, (1 << 12) | (1 << 11)); WRITE_VREG(DOS_SW_RESET0, 0); READ_VREG(DOS_SW_RESET0); READ_VREG(DOS_SW_RESET0); READ_VREG(DOS_SW_RESET0); } else { /* #else */ WRITE_MPEG_REG(RESET0_REGISTER, RESET_VCPU | RESET_CCPU); /* additional cbus dummy register reading for timing control */ READ_MPEG_REG(RESET0_REGISTER); READ_MPEG_REG(RESET0_REGISTER); READ_MPEG_REG(RESET0_REGISTER); READ_MPEG_REG(RESET0_REGISTER); } /* #endif */ #ifdef CONFIG_WAKELOCK amvdec_wake_unlock(); #endif }