void cec_enable_irq(void)
{
aml_write_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR, aml_read_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR) & ~(1 << 23));
aml_write_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_MASK, aml_read_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_MASK) | (1 << 23));
hdmi_print(INF, CEC "enable:int mask:0x%x\n", aml_read_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_MASK));
}
static void wait_uart_empty(void)
{
unsigned int count=0;
do{
if((aml_read_reg32(P_UART0_STATUS) & (1<<22)) == 0)
udelay(4);
else
break;
count++;
}while(count<2000000);
count=0;
do{
if((aml_read_reg32(P_UART1_STATUS) & (1<<22)) == 0)
udelay(4);
else
break;
count++;
}while(count<2000000);
count=0;
do{
if((aml_read_reg32(P_AO_UART_STATUS) & (1<<22)) == 0)
udelay(4);
else
break;
count++;
}while(count<2000000);
}
int __init meson_cpu_version_init(void)
{
unsigned int version,ver;
unsigned int *version_map;
meson_cpu_version[MESON_CPU_VERSION_LVL_MAJOR] =
aml_read_reg32(P_ASSIST_HW_REV);
#ifndef CONFIG_MESON_TRUSTZONE
version_map = (unsigned int *)IO_BOOTROM_BASE;
meson_cpu_version[MESON_CPU_VERSION_LVL_MISC] = version_map[1];
#else
meson_cpu_version[MESON_CPU_VERSION_LVL_MISC] = meson_read_socrev1();
#endif
version = aml_read_reg32(P_METAL_REVISION);
switch (version) {
case 0x11111111:
ver = 0xA;
break;
default:/*changed?*/
ver = 0xB;
break;
}
meson_cpu_version[MESON_CPU_VERSION_LVL_MINOR] = ver;
printk(KERN_INFO "Meson chip version = Rev%X (%X:%X - %X:%X)\n", ver,
meson_cpu_version[MESON_CPU_VERSION_LVL_MAJOR],
meson_cpu_version[MESON_CPU_VERSION_LVL_MINOR],
meson_cpu_version[MESON_CPU_VERSION_LVL_PACK],
meson_cpu_version[MESON_CPU_VERSION_LVL_MISC]
);
return 0;
}
/*as use the spin_lock,
*1--there is no sleep,
*2--it is better to shorter the time,
*/
int amcsi_isr(struct tvin_frontend_s *fe, unsigned int hcnt)
{
struct amcsi_dev_s *devp = container_of(fe, amcsi_dev_t, frontend);
unsigned data1 = 0;
unsigned data2 = 0;
am_csi2_frame_t frame;
frame.w = aml_get_reg32_bits( P_CSI2_PIC_SIZE_STAT, 0, 16);
frame.h = aml_get_reg32_bits( P_CSI2_PIC_SIZE_STAT, 16,16);
frame.err = aml_read_reg32( P_CSI2_ERR_STAT0 );
data1 = aml_read_reg32( P_CSI2_DATA_TYPE_IN_MEM);
data2 = aml_read_reg32( P_CSI2_GEN_STAT0);
if(frame.err){
mipi_error("%s,error---pixel cnt:%d, line cnt:%d. error state:0x%x.mem type:0x%x, status:0x%x\n",
__func__, frame.w, frame.h, frame.err, data1, data2);
devp->overflow_cnt ++;
aml_write_reg32( P_CSI2_ERR_STAT0, 0);
}
if( devp->overflow_cnt > 4){
DPRINT("should reset mipi\n");
devp->overflow_cnt = 0;
return 0;
}
devp->reset = 0;
return 0;
}
void cec_disable_irq(void)
{
//Disable irq
aml_write_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_MASK, aml_read_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_MASK) & ~(1 << 23));
//Clear the interrupt
aml_write_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR, aml_read_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR) | (1 << 23));
hdmi_print(INF, CEC "disable:int mask:0x%x\n", aml_read_reg32(P_SYS_CPU_0_IRQ_IN1_INTR_MASK));
}
static void set_pll_lvds(Lcd_Config_t *pConf)
{
PRINT_INFO("%s\n", __FUNCTION__);
vclk_set_encl_lvds(pDev->lcd_info.mode, pConf->lvds_mlvds_config.lvds_config->dual_port);
aml_write_reg32( P_HHI_VIID_DIVIDER_CNTL, ((aml_read_reg32(P_HHI_VIID_DIVIDER_CNTL) & ~(0x7 << 8)) | (2 << 8) | (0<<10)) );
aml_write_reg32(P_LVDS_GEN_CNTL, (aml_read_reg32(P_LVDS_GEN_CNTL)| (1 << 3) | (3<< 0)));
}
static inline void _enable_vsync_interrupt(void)
{
if ((aml_read_reg32(P_ENCT_VIDEO_EN) & 1) || (aml_read_reg32(P_ENCL_VIDEO_EN) & 1)) {
aml_write_reg32(P_VENC_INTCTRL, 0x200);
}else {
aml_write_reg32(P_VENC_INTCTRL, 0x2);
}
}
int gpio_amlogic_direction_output(struct gpio_chip *chip,unsigned offset, int value)
{
unsigned int reg,bit;
if(offset==GPIO_BSD_EN){
aml_clr_reg32_mask(P_PREG_PAD_GPIO0_O,1<<29);
#ifndef CONFIG_MESON_TRUSTZONE
aml_set_reg32_mask(P_AO_SECURE_REG0,1<<0);
#else
meson_secure_reg_write(P_AO_SECURE_REG0, meson_secure_reg_read(P_AO_SECURE_REG0) | (1<<0));
#endif
if(value)
aml_set_reg32_mask(P_PREG_PAD_GPIO0_O,1<<31);//out put high
else
aml_clr_reg32_mask(P_PREG_PAD_GPIO0_O,1<<31);//out put low
aml_clr_reg32_mask(P_PREG_PAD_GPIO0_O,1<<30);//out put enable
return 0;
}
if(offset==GPIO_TEST_N){
if(value)
aml_set_reg32_mask(P_AO_GPIO_O_EN_N,1<<31);//out put high
else
aml_clr_reg32_mask(P_AO_GPIO_O_EN_N,1<<31);//out put low
#ifndef CONFIG_MESON_TRUSTZONE
aml_set_reg32_mask(P_AO_SECURE_REG0,1);// out put enable
#else
meson_secure_reg_write(P_AO_SECURE_REG0, meson_secure_reg_read(P_AO_SECURE_REG0) | (1<<0));
#endif
return 0;
}
if(value){
reg=GPIO_REG(amlogic_pins[offset].out_value_reg_bit);
bit=GPIO_BIT(amlogic_pins[offset].out_value_reg_bit);
aml_set_reg32_mask(p_gpio_output_addr[reg],1<<bit);
gpio_print("out reg=%x,value=%x\n",p_gpio_output_addr[reg],aml_read_reg32(p_gpio_output_addr[reg]));
}
else{
reg=GPIO_REG(amlogic_pins[offset].out_value_reg_bit);
bit=GPIO_BIT(amlogic_pins[offset].out_value_reg_bit);
aml_clr_reg32_mask(p_gpio_output_addr[reg],1<<bit);
gpio_print("out reg=%x,value=%x\n",p_gpio_output_addr[reg],aml_read_reg32(p_gpio_output_addr[reg]));
}
reg=GPIO_REG(amlogic_pins[offset].out_en_reg_bit);
bit=GPIO_BIT(amlogic_pins[offset].out_en_reg_bit);
aml_clr_reg32_mask(p_gpio_oen_addr[reg],1<<bit);
gpio_print("==%s==%d\n",__FUNCTION__,__LINE__);
gpio_print("oen reg=%x,value=%x\n",p_gpio_oen_addr[reg],aml_read_reg32(p_gpio_oen_addr[reg]));
gpio_print("value=%d\n",value);
return 0;
}
// change tv mode and show logo immediatly when hdmi pluged
int set_mode_and_show_logo(int hpd_state) {
int value;
logo_object_t* plogo = get_current_logo_obj();
if((plogo->para.vout_mode & VMODE_MODE_BIT_MASK) > VMODE_4K2K_SMPTE) {
return 0; // MID
}
printk("hdmi detect: %s.\n", (hpd_state==1)?"plug":"unplug");
// osd2 freescale enable, the logo is shown on osd2, reset freescale.
value = aml_read_reg32(P_VPP_OSD_SC_CTRL0) & 0xb;
if(value == 0x9) {
vmode_t cur_mode;
if (hpd_state == 0){
cur_mode = cvbsmode_hdmionly;
}
else{
cur_mode = hdmimode_hdmionly;
}
if(tvmode != cur_mode) {
tvmode = cur_mode;
osd_enable_hw(0, plogo->para.output_dev_type);
set_current_vmode(cur_mode);
vout_notifier_call_chain(VOUT_EVENT_MODE_CHANGE,&cur_mode) ;
set_osd_freescaler(plogo->para.output_dev_type, plogo, cur_mode);
}
}
return 1;
}
static void backlight_power_ctrl(Bool_t status)
{
PRINT_INFO("%s(): bl_status=%s, data_status=%s, bl_level=%u\n", __FUNCTION__, (bl_status ? "ON" : "OFF"), (data_status ? "ON" : "OFF"), bl_level);
if( status == ON ){
if ((bl_status == ON) || (data_status == OFF) || (bl_level == 0))
return;
aml_set_reg32_bits(P_LED_PWM_REG0, 1, 12, 2);
mdelay(20);
#if (BL_CTL==BL_CTL_GPIO)
//BL_EN -> GPIOD_1: 1
gpio_out(PAD_GPIOD_1, 1);
#elif (BL_CTL==BL_CTL_PWM)
aml_set_reg32_bits(P_PWM_MISC_REG_CD, PWM_PRE_DIV, 16, 7);
aml_set_reg32_bits(P_PWM_MISC_REG_CD, 1, 23, 1);
aml_set_reg32_bits(P_PWM_MISC_REG_CD, 1, 1, 1); //enable pwm_d
aml_write_reg32(P_PERIPHS_PIN_MUX_2, aml_read_reg32(P_PERIPHS_PIN_MUX_2) | (1<<3)); //enable pwm pinmux
#endif
}
else{
if (bl_status == OFF)
return;
#if (BL_CTL==BL_CTL_GPIO)
gpio_out(PAD_GPIOD_1, 0);
#elif (BL_CTL==BL_CTL_PWM)
aml_set_reg32_bits(P_PWM_MISC_REG_CD, 0, 1, 1); //disable pwm_d
#endif
}
bl_status = status;
printk(KERN_INFO "%s() Power %s\n", __FUNCTION__, (status ? "ON" : "OFF"));
}
int __init meson_cpu_version_init(void)
{
unsigned int version,ver;
unsigned int *version_map;
meson_cpu_version[MESON_CPU_VERSION_LVL_MAJOR] =
aml_read_reg32(P_ASSIST_HW_REV);
version_map = (unsigned int *)IO_BOOTROM_BASE;
meson_cpu_version[MESON_CPU_VERSION_LVL_MISC] = version_map[1];
//version = aml_read_reg32(P_METAL_REVISION);
version = version_map[1];
switch (version) {
case 0x18D7:
ver = 0xA;
break;
case 0x1C64:
ver = 0xB;
break;
default:/*changed?*/
ver = 0xC;
break;
}
meson_cpu_version[MESON_CPU_VERSION_LVL_MINOR] = ver;
printk(KERN_INFO "Meson chip version = Rev%X (%X:%X - %X:%X)\n", ver,
meson_cpu_version[MESON_CPU_VERSION_LVL_MAJOR],
meson_cpu_version[MESON_CPU_VERSION_LVL_MINOR],
meson_cpu_version[MESON_CPU_VERSION_LVL_PACK],
meson_cpu_version[MESON_CPU_VERSION_LVL_MISC]
);
return 0;
}
void tx_irq_handle(void)
{
unsigned tx_status = aocec_rd_reg(CEC_TX_MSG_STATUS);
switch (tx_status)
{
case TX_DONE:
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
case TX_BUSY:
aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT);
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
case TX_ERROR:
if (cec_msg_dbg_en == 1)
hdmi_print(INF, CEC "TX ERROR!!!\n");
if (RX_ERROR == aocec_rd_reg(CEC_RX_MSG_STATUS))
{
cec_hw_reset();
}
else
{
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
}
//aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
default:
break;
}
aml_write_reg32(P_AO_CEC_INTR_CLR, aml_read_reg32(P_AO_CEC_INTR_CLR) | (1 << 1));
//aml_write_reg32(P_AO_CEC_INTR_MASKN, aml_read_reg32(P_AO_CEC_INTR_MASKN) | (1 << 2));
}
static unsigned int aml_read_reg32_d(unsigned int addr)
{
unsigned int val = 0;
val = aml_read_reg32(addr);
//printk("R: 0x%08x 0x%08x\n", addr, val);
return val;
}
void meson_common_restart(char mode,const char *cmd)
{
u32 reboot_reason = MESON_NORMAL_BOOT;
if (cmd) {
if (strcmp(cmd, "charging_reboot") == 0)
reboot_reason = MESON_CHARGING_REBOOT;
else if (strcmp(cmd, "update") == 0)
reboot_reason = MESON_UPDATE_REBOOT;
else if (strcmp(cmd, "report_crash") == 0)
reboot_reason = MESON_CRASH_REBOOT;
else if (strcmp(cmd, "factory_testl_reboot") == 0)
reboot_reason = MESON_FACTORY_TEST_REBOOT;
else if (strcmp(cmd, "switch_system") == 0)
reboot_reason = MESON_SYSTEM_SWITCH_REBOOT;
else if (strcmp(cmd, "safe_mode") == 0)
reboot_reason = MESON_SAFE_REBOOT;
else if (strcmp(cmd, "lock_system") == 0)
reboot_reason = MESON_LOCK_REBOOT;
else if (strcmp(cmd, "usb_burner_reboot") == 0)
reboot_reason = MESON_USB_BURNER_REBOOT;
else if (strcmp(cmd, "uboot_suspend") == 0)
reboot_reason = MESON_UBOOT_SUSPEND;
else if (strcmp(cmd, "androidv2") == 0)
reboot_reason = MESON_REBOOT_ANDROIDV2;
}
aml_write_reg32(P_AO_RTI_STATUS_REG1, reboot_reason);
printk("reboot_reason(0x%x) = 0x%x\n", P_AO_RTI_STATUS_REG1, aml_read_reg32(P_AO_RTI_STATUS_REG1));
arch_reset(mode,cmd);
}
static void set_control_lvds(Lcd_Config_t *pConf)
{
PRINT_INFO("%s\n", __FUNCTION__);
if (lvds_repack_flag)
lvds_repack = (pConf->lvds_mlvds_config.lvds_config->lvds_repack) & 0x1;
pn_swap = (pConf->lvds_mlvds_config.lvds_config->pn_swap) & 0x1;
dual_port = (pConf->lvds_mlvds_config.lvds_config->dual_port) & 0x1;
if (port_reverse_flag)
port_reverse = (pConf->lvds_mlvds_config.lvds_config->port_reverse) & 0x1;
if (bit_num_flag) {
switch (pConf->lcd_basic.lcd_bits) {
case 10: bit_num=0; break;
case 8: bit_num=1; break;
case 6: bit_num=2; break;
case 4: bit_num=3; break;
default: bit_num=1; break;
}
}
aml_write_reg32(P_MLVDS_CONTROL, (aml_read_reg32(P_MLVDS_CONTROL) & ~(1 << 0))); //disable mlvds
aml_write_reg32(P_LVDS_PACK_CNTL_ADDR,
( lvds_repack<<0 ) | // repack
( port_reverse?(0<<2):(1<<2)) | // odd_even
( 0<<3 ) | // reserve
( 0<<4 ) | // lsb first
( pn_swap<<5 ) | // pn swap
( dual_port<<6 ) | // dual port
( 0<<7 ) | // use tcon control
( bit_num<<8 ) | // 0:10bits, 1:8bits, 2:6bits, 3:4bits.
( 0<<10 ) | //r_select //0:R, 1:G, 2:B, 3:0
( 1<<12 ) | //g_select //0:R, 1:G, 2:B, 3:0
( 2<<14 )); //b_select //0:R, 1:G, 2:B, 3:0;
}
void cec_disable_irq(void)
{
// disable all AO_CEC interrupt sources
aml_set_reg32_bits(P_AO_CEC_INTR_MASKN, 0x0, 0, 3);
cec_int_disable_flag = 1;
hdmi_print(INF, CEC "disable:int mask:0x%x\n", aml_read_reg32(P_AO_CEC_INTR_MASKN));
}
static inline void setup_color_mode(const color_bit_define_t *color,u32 reg)
{
u32 data32;
data32 = aml_read_reg32(reg)&(~(0xf<<8));
data32 |= color->hw_blkmode<< 8; /* osd_blk_mode */
aml_write_reg32(reg, data32);
}
int cec_ll_rx( unsigned char *msg, unsigned char *len)
{
int i;
int ret = -1;
int pos;
if ((RX_DONE != aocec_rd_reg(CEC_RX_MSG_STATUS)) || (1 != aocec_rd_reg(CEC_RX_NUM_MSG)))
{
//cec_rx_buf_check();
aml_write_reg32(P_AO_CEC_INTR_CLR, aml_read_reg32(P_AO_CEC_INTR_CLR) | (1 << 2));
aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
return ret;
}
*len = aocec_rd_reg(CEC_RX_MSG_LENGTH) + 1;
for (i = 0; i < (*len) && i < MAX_MSG; i++)
{
msg[i]= aocec_rd_reg(CEC_RX_MSG_0_HEADER +i);
}
ret = aocec_rd_reg(CEC_RX_MSG_STATUS);
if (cec_msg_dbg_en == 1)
{
pos = 0;
pos += sprintf(msg_log_buf + pos, "CEC: rx msg len: %d dat: ", *len);
for (i = 0; i < (*len); i++)
{
pos += sprintf(msg_log_buf + pos, "%02x ", msg[i]);
}
pos += sprintf(msg_log_buf + pos, "\n");
msg_log_buf[pos] = '\0';
hdmi_print(INF, CEC "%s", msg_log_buf);
}
//cec_rx_buf_check();
aml_write_reg32(P_AO_CEC_INTR_CLR, aml_read_reg32(P_AO_CEC_INTR_CLR) | (1 << 2));
aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
//aml_write_reg32(P_AO_CEC_INTR_CLR, aml_read_reg32(P_AO_CEC_INTR_CLR) | (1 << 2));
return ret;
}
// In order to prevent system hangup, add check_cts_hdmi_sys_clk_status() to check
static void check_cts_hdmi_sys_clk_status(void)
{
int i;
for(i = 0; i < GATE_NUM; i++){
if(!(aml_read_reg32(CBUS_REG_ADDR(hdmi_gate[i].cbus_addr)) & (1<<hdmi_gate[i].gate_bit))){
aml_set_reg32_bits(CBUS_REG_ADDR(hdmi_gate[i].cbus_addr), 1, hdmi_gate[i].gate_bit, 1);
}
}
}
static int stop_rdma(char channel)
{
char intr_bit=8*channel;
u32 data32 = 0x0;
data32 = aml_read_reg32(P_RDMA_ACCESS_AUTO);
data32 &= ~(0x1 << intr_bit); // [23: 16] interrupt inputs enable mask for auto-start 1: vsync int bit 0
aml_write_reg32(P_RDMA_ACCESS_AUTO, data32);
return 0;
}
// viu_channel_sel: 1 or 2
// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
int set_viu_path(unsigned viu_channel_sel, viu_type_e viu_type_sel)
{
if((viu_channel_sel > 2) || (viu_channel_sel == 0))
return -1;
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
printk("VPU_VIU_VENC_MUX_CTRL: 0x%x\n", aml_read_reg32(P_VPU_VIU_VENC_MUX_CTRL));
if(viu_channel_sel == 1){
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
printk("viu chan = 1\n");
}
else{
//viu_channel_sel ==2
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
printk("viu chan = 2\n");
}
printk("VPU_VIU_VENC_MUX_CTRL: 0x%x\n", aml_read_reg32(P_VPU_VIU_VENC_MUX_CTRL));
#endif
return 0;
}
// In order to prevent system hangup, add check_cts_hdmi_sys_clk_status() to check
static void check_cts_hdmi_sys_clk_status(void)
{
int i;
for(i = 0; i < GATE_NUM; i++){
if(!(aml_read_reg32(CBUS_REG_ADDR(hdmi_gate[i].cbus_addr)) & (1<<hdmi_gate[i].gate_bit))){
printk("HDMI Gate Clock is off, turn on now\n");
aml_set_reg32_bits(CBUS_REG_ADDR(hdmi_gate[i].cbus_addr), 1, hdmi_gate[i].gate_bit, 1);
}
}
}
static void set_tcon_ttl(Lcd_Config_t *pConf)
{
Lcd_Timing_t *tcon_adr = &(pConf->lcd_timing);
//set_lcd_gamma_table_ttl(pConf->lcd_effect.GammaTableR, LCD_H_SEL_R);
//set_lcd_gamma_table_ttl(pConf->lcd_effect.GammaTableG, LCD_H_SEL_G);
//set_lcd_gamma_table_ttl(pConf->lcd_effect.GammaTableB, LCD_H_SEL_B);
aml_write_reg32(P_L_GAMMA_CNTL_PORT, 0);//pConf->lcd_effect.gamma_cntl_port);
//aml_write_reg32(P_GAMMA_VCOM_HSWITCH_ADDR, pConf->lcd_effect.gamma_vcom_hswitch_addr);
aml_write_reg32(P_L_RGB_BASE_ADDR, 0xf0);//pConf->lcd_effect.rgb_base_addr);
aml_write_reg32(P_L_RGB_COEFF_ADDR, 0x74a);//pConf->lcd_effect.rgb_coeff_addr);
//aml_write_reg32(P_POL_CNTL_ADDR, pConf->lcd_timing.pol_cntl_addr);
if (pConf->lcd_basic.lcd_bits == 8)
aml_write_reg32(P_L_DITH_CNTL_ADDR, 0x400);
else
aml_write_reg32(P_L_DITH_CNTL_ADDR, 0x600);
aml_write_reg32(P_L_STH1_HS_ADDR, tcon_adr->sth1_hs_addr);
aml_write_reg32(P_L_STH1_HE_ADDR, tcon_adr->sth1_he_addr);
aml_write_reg32(P_L_STH1_VS_ADDR, tcon_adr->sth1_vs_addr);
aml_write_reg32(P_L_STH1_VE_ADDR, tcon_adr->sth1_ve_addr);
aml_write_reg32(P_L_OEH_HS_ADDR, tcon_adr->oeh_hs_addr);
aml_write_reg32(P_L_OEH_HE_ADDR, tcon_adr->oeh_he_addr);
aml_write_reg32(P_L_OEH_VS_ADDR, tcon_adr->oeh_vs_addr);
aml_write_reg32(P_L_OEH_VE_ADDR, tcon_adr->oeh_ve_addr);
aml_write_reg32(P_L_VCOM_HSWITCH_ADDR, tcon_adr->vcom_hswitch_addr);
aml_write_reg32(P_L_VCOM_VS_ADDR, tcon_adr->vcom_vs_addr);
aml_write_reg32(P_L_VCOM_VE_ADDR, tcon_adr->vcom_ve_addr);
aml_write_reg32(P_L_CPV1_HS_ADDR, tcon_adr->cpv1_hs_addr);
aml_write_reg32(P_L_CPV1_HE_ADDR, tcon_adr->cpv1_he_addr);
aml_write_reg32(P_L_CPV1_VS_ADDR, tcon_adr->cpv1_vs_addr);
aml_write_reg32(P_L_CPV1_VE_ADDR, tcon_adr->cpv1_ve_addr);
aml_write_reg32(P_L_STV1_HS_ADDR, tcon_adr->stv1_hs_addr);
aml_write_reg32(P_L_STV1_HE_ADDR, tcon_adr->stv1_he_addr);
aml_write_reg32(P_L_STV1_VS_ADDR, tcon_adr->stv1_vs_addr);
aml_write_reg32(P_L_STV1_VE_ADDR, tcon_adr->stv1_ve_addr);
aml_write_reg32(P_L_OEV1_HS_ADDR, tcon_adr->oev1_hs_addr);
aml_write_reg32(P_L_OEV1_HE_ADDR, tcon_adr->oev1_he_addr);
aml_write_reg32(P_L_OEV1_VS_ADDR, tcon_adr->oev1_vs_addr);
aml_write_reg32(P_L_OEV1_VE_ADDR, tcon_adr->oev1_ve_addr);
aml_write_reg32(P_L_INV_CNT_ADDR, tcon_adr->inv_cnt_addr);
aml_write_reg32(P_L_TCON_MISC_SEL_ADDR, tcon_adr->tcon_misc_sel_addr);
aml_write_reg32(P_L_DUAL_PORT_CNTL_ADDR, tcon_adr->dual_port_cntl_addr);
aml_write_reg32(P_VPP_MISC, aml_read_reg32(P_VPP_MISC) & ~(VPP_OUT_SATURATE));
}
int meson_cpu_kill(unsigned int cpu)
{
unsigned int value;
unsigned int offset=(cpu<<3);
do{
udelay(10);
value=aml_read_reg32(MESON_CPU_POWER_CTRL_REG);
}while((value&(3<<offset)) != (3<<offset));
udelay(10);
meson_set_cpu_power_ctrl(cpu, 0);
return 1;
}
void cec_hw_reset(void)
{
aml_write_reg32(P_HDMI_CTRL_PORT, aml_read_reg32(P_HDMI_CTRL_PORT)|(1<<16));
hdmi_wr_reg(OTHER_BASE_ADDR+HDMI_OTHER_CTRL0, 0xc); //[3]cec_creg_sw_rst [2]cec_sys_sw_rst
hdmi_wr_reg(CEC0_BASE_ADDR+CEC_TX_CLEAR_BUF, 0x1);
hdmi_wr_reg(CEC0_BASE_ADDR+CEC_RX_CLEAR_BUF, 0x1);
//mdelay(10);
{//Delay some time
int i = 10;
while(i--);
}
hdmi_wr_reg(CEC0_BASE_ADDR+CEC_TX_CLEAR_BUF, 0x0);
hdmi_wr_reg(CEC0_BASE_ADDR+CEC_RX_CLEAR_BUF, 0x0);
hdmi_wr_reg(OTHER_BASE_ADDR+HDMI_OTHER_CTRL0, 0x0);
aml_write_reg32(P_HDMI_CTRL_PORT, aml_read_reg32(P_HDMI_CTRL_PORT)&(~(1<<16)));
hdmi_wr_reg(CEC0_BASE_ADDR+CEC_CLOCK_DIV_H, 0x00 );
hdmi_wr_reg(CEC0_BASE_ADDR+CEC_CLOCK_DIV_L, 0xf0 );
hdmi_wr_reg(CEC0_BASE_ADDR+CEC_LOGICAL_ADDR0, (0x1 << 4) | cec_global_info.my_node_index);
hdmi_print(INF, CEC "hw reset :logical addr:0x%x\n", hdmi_rd_reg(CEC0_BASE_ADDR+CEC_LOGICAL_ADDR0));
}
static vmode_t nulldisp_validate_vmode(char *mode)
{
const vinfo_t *info = get_valid_vinfo(mode);
int viu1_select = aml_read_reg32(P_VPU_VIU_VENC_MUX_CTRL)&0x3;
DisableVideoLayer();
aml_set_reg32_bits (P_VPU_VIU_VENC_MUX_CTRL, (viu1_select+1)&0x3, 2, 2); //viu2_select should be different from viu1_select (to fix viu1 video smooth problem)
if (info)
return info->mode;
return VMODE_MAX;
}
unsigned long hdmi_rd_reg(unsigned long addr)
{
unsigned long data;
check_cts_hdmi_sys_clk_status();
// WRITE_APB_REG(HDMI_ADDR_PORT, addr);
// WRITE_APB_REG(HDMI_ADDR_PORT, addr);
aml_write_reg32(P_HDMI_ADDR_PORT, addr);
aml_write_reg32(P_HDMI_ADDR_PORT, addr);
// data = READ_APB_REG(HDMI_DATA_PORT);
data = aml_read_reg32(P_HDMI_DATA_PORT);
return (data);
}
static void wait_uart_empty()
{
do{
if((aml_read_reg32(P_UART0_STATUS) & (1<<22)) == 0)
udelay(4);
else
break;
}while(1);
do{
if((aml_read_reg32(P_UART1_STATUS) & (1<<22)) == 0)
udelay(4);
else
break;
}while(1);
do{
if((aml_read_reg32(P_AO_UART_STATUS) & (1<<22)) == 0)
udelay(4);
else
break;
}while(1);
}
int cec_ll_rx( unsigned char *msg, unsigned char *len)
{
unsigned char i;
unsigned char rx_status;
unsigned char data;
unsigned char msg_log_buf[128];
int pos;
unsigned char n;
unsigned char *msg_start = msg;
int rx_msg_length;
if(RX_DONE != aocec_rd_reg(CEC_RX_MSG_STATUS)){
aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
return -1;
}
if(1 != aocec_rd_reg(CEC_RX_NUM_MSG)){
aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
return -1;
}
rx_msg_length = aocec_rd_reg(CEC_RX_MSG_LENGTH) + 1;
aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
for (i = 0; i < rx_msg_length && i < MAX_MSG; i++) {
data = aocec_rd_reg(CEC_RX_MSG_0_HEADER +i);
*msg = data;
msg++;
}
*len = rx_msg_length;
rx_status = aocec_rd_reg(CEC_RX_MSG_STATUS);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
aml_write_reg32(P_AO_CEC_INTR_CLR, aml_read_reg32(P_AO_CEC_INTR_CLR) | (1 << 2));
if(cec_msg_dbg_en == 1){
pos = 0;
pos += sprintf(msg_log_buf + pos, "CEC: rx msg len: %d dat: ", rx_msg_length);
for(n = 0; n < rx_msg_length; n++) {
pos += sprintf(msg_log_buf + pos, "%02x ", msg_start[n]);
}
pos += sprintf(msg_log_buf + pos, "\n");
msg_log_buf[pos] = '\0';
hdmi_print(INF, CEC "%s", msg_log_buf);
}
return rx_status;
}
static void set_tcon_lvds(Lcd_Config_t *pConf)
{
vpp_set_matrix_ycbcr2rgb(2, 0);
aml_write_reg32(P_ENCL_VIDEO_RGBIN_CTRL, 3);
aml_write_reg32(P_L_RGB_BASE_ADDR, 0);
aml_write_reg32(P_L_RGB_COEFF_ADDR, 0x400);
if (pConf->lcd_basic.lcd_bits == 8)
aml_write_reg32(P_L_DITH_CNTL_ADDR, 0x400);
else if (pConf->lcd_basic.lcd_bits == 6)
aml_write_reg32(P_L_DITH_CNTL_ADDR, 0x600);
else
aml_write_reg32(P_L_DITH_CNTL_ADDR, 0);
aml_write_reg32(P_VPP_MISC, aml_read_reg32(P_VPP_MISC) & ~(VPP_OUT_SATURATE));
}