void process_data(AXI_STREAM &SRC, AXI_STREAM &DST, ap_uint<32> *dbg)
{
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE axis port=SRC
#pragma HLS INTERFACE axis port=DST
static float buffer[MAX_BUFFER];
#pragma HLS RESOURCE variable=buffer core=RAM_2P_BRAM
static uint32_t packet_received = 0;
static uint32_t packet_processed = 0;
static uint32_t packet_length = 0;
di_axis<32> src_tmp;
di_axis<32> dst_tmp;
*dbg = packet_length;
//Read input.
Read_Input: while (packet_length < MAX_BUFFER)
{
#pragma HLS PIPELINE II=1
src_tmp = SRC.read();
ap_wait();
buffer[packet_length] = src_tmp.data + 0.1 * packet_length;
packet_length = packet_length + 1;
if (src_tmp.last.to_int() == 1)
break;
}
ap_wait();
//Write output.
Write_Output: for (int i = 0; i < packet_length; i++)
{
#pragma HLS PIPELINE II=1
dst_tmp.data = buffer[i];
dst_tmp.strb = 15;
dst_tmp.last = (i == (packet_length - 1)) ? 1 : 0;
DST.write(dst_tmp);
if (i == (packet_length - 1))
packet_length = 0;
}
}
Event * InputThread::wait_for_event() {
Event * event = fifo.pop();
if (event==NULL) {
ap_wait(fifo.handle());
event = fifo.pop();
}
FXASSERT(event);
return event;
}
Event * InputThread::wait_for_packet() {
Event * event=NULL;
do {
event=fifo.pop();
if (event) return event;
Packet * packet = packetpool.pop();
if (packet) return packet;
ap_wait(fifo.handle(),packetpool.handle());
}
while(1);
return NULL;
}
Packet * InputThread::get_packet() {
FXuchar type;
do {
type = fifo.peek();
if (type!=Buffer && type!=AP_INVALID){
return NULL;
}
Packet * packet = packetpool.pop();
if (packet) return packet;
ap_wait(packetpool.handle(),fifo.handle());
}
while(1);
return NULL;
}
Event* InputThread::get_packet() {
Event * event=NULL;
event = DecoderPacket::get();
if (event) return event;
if (fifo.peek()!=Invalid) return NULL;
FXint result = ap_wait(DecoderPacket::handle(),fifo.handle());
//fxmessage("get packet result==%d\n",result);
if (result==1) {
event=DecoderPacket::get();
}
return event;
}
