/*
* Attach to a device instance. Setup the public definition
* of how much per-node space we need and setup the private
* phy tables that have rate control parameters. These tables
* are normally part of the Atheros hal but are not included
* in our hal as the rate control data was not being used and
* was considered proprietary (at the time).
*/
struct atheros_softc *
ath_rate_attach(struct ath_hal *ah)
{
struct atheros_softc *asc;
RC_OS_MALLOC(&asc, sizeof(struct atheros_softc), RATECTRL_MEMTAG);
if (asc == NULL)
return NULL;
OS_MEMZERO(asc, sizeof(struct atheros_softc));
/*
* Use the magic number to figure out the chip type.
* There's probably a better way to do this but for
* now this suffices.
*
* NB: We don't have a separate set of tables for the
* 5210; treat it like a 5211 since it has the same
* tx descriptor format and (hopefully) sufficiently
* similar operating characteristics to work ok.
*/
switch (ah->ah_magic) {
#ifdef AH_SUPPORT_AR5212
case 0x19570405:
case 0x19541014: /* 5212 */
ar5212AttachRateTables(asc);
asc->prate_maprix = ar5212_rate_maprix;
break;
#endif
case 0x19641014: /* 5416 */
case 0x19741014: /* 9300 */
ar5416AttachRateTables(asc);
asc->prate_maprix = ar5416_rate_maprix;
break;
default:
ASSERT(0);
break;
}
/* Save Maximum TX Trigger Level (used for 11n) */
ath_hal_getcapability(ah, HAL_CAP_TX_TRIG_LEVEL_MAX, 0, &asc->txTrigLevelMax);
/* return alias for atheros_softc * */
return asc;
}
struct ath_ratectrl *
ath_rate_attach(struct ath_softc_tgt *sc)
{
struct atheros_softc *asc;
asc = adf_os_mem_alloc(sizeof(struct atheros_softc));
if (asc == NULL)
return NULL;
adf_os_mem_set(asc, 0, sizeof(struct atheros_softc));
asc->arc.arc_space = sizeof(struct atheros_node);
ar5416AttachRateTables(asc);
asc->tx_chainmask = 1;
return &asc->arc;
}
