void all_led_on(void){
unsigned int gpio;
gpio = ar7240_reg_rd(AR7240_GPIO_OUT);
#if defined(CONFIG_FOR_OMY)
SETBITVAL(gpio, GPIO_WPS_LED_BIT, GPIO_SYS_LED_ON);
#elif defined(CONFIG_FOR_TPLINK_MR3020_V1)
SETBITVAL(gpio, GPIO_WPS_LED_BIT, GPIO_WPS_LED_ON);
SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
SETBITVAL(gpio, GPIO_ETH_LED_BIT, GPIO_ETH_LED_ON);
#elif defined(CONFIG_FOR_TPLINK_WR703N_V1) || defined(CONFIG_FOR_TPLINK_WR720N_V3) || defined (CONFIG_FOR_TPLINK_WR710N_V1)
SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
#elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2)
SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
SETBITVAL(gpio, GPIO_ETH_LED_BIT, GPIO_ETH_LED_ON);
#elif defined(CONFIG_FOR_TPLINK_MR10U_V1) || defined(CONFIG_FOR_TPLINK_MR13U_V1)
SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
#elif defined(CONFIG_FOR_TPLINK_WR740N_V4) || defined(CONFIG_FOR_TPLINK_MR3220_V2)
SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
SETBITVAL(gpio, GPIO_LAN1_LED_BIT, GPIO_LAN1_LED_ON);
SETBITVAL(gpio, GPIO_LAN2_LED_BIT, GPIO_LAN2_LED_ON);
SETBITVAL(gpio, GPIO_LAN3_LED_BIT, GPIO_LAN3_LED_ON);
SETBITVAL(gpio, GPIO_LAN4_LED_BIT, GPIO_LAN4_LED_ON);
SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
SETBITVAL(gpio, GPIO_QSS_LED_BIT, GPIO_QSS_LED_ON);
#ifdef CONFIG_FOR_TPLINK_MR3220_V2
SETBITVAL(gpio, GPIO_USB_LED_BIT, GPIO_USB_LED_ON);
#endif
#elif defined(CONFIG_FOR_DLINK_DIR505_A1)
SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
#elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
SETBITVAL(gpio, GPIO_WAN_LED_BIT, GPIO_WAN_LED_ON);
SETBITVAL(gpio, GPIO_LAN1_LED_BIT, GPIO_LAN1_LED_ON);
SETBITVAL(gpio, GPIO_LAN2_LED_BIT, GPIO_LAN2_LED_ON);
#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
#elif defined(CONFIG_FOR_DRAGINO_V2) || defined(CONFIG_FOR_MESH_POTATO_V2)
SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
SETBITVAL(gpio, GPIO_WAN_LED_BIT, GPIO_WAN_LED_ON);
SETBITVAL(gpio, GPIO_LAN_LED_BIT, GPIO_LAN_LED_ON);
SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
#elif defined(CONFIG_FOR_GL_INET)
SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
SETBITVAL(gpio, GPIO_LAN_LED_BIT, GPIO_LAN_LED_ON);
#else
#error "Custom GPIO in all_led_on() not defined!"
#endif
ar7240_reg_wr(AR7240_GPIO_OUT, gpio);
}
static void ar7240_spi_poll(){
int rd;
do {
ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS);
ar7240_spi_bit_banger(AR7240_SPI_CMD_RD_STATUS);
ar7240_spi_delay_8();
rd = (ar7240_reg_rd(AR7240_SPI_RD_STATUS) & 1);
} while(rd);
}
/* Return the value present in the watchdog register */
static inline uint32_t
ar7240_get_wd_timer(void)
{
uint32_t val;
val = (uint32_t)ar7240_reg_rd(AR7240_WATCHDOG_TMR);
val = (val * USEC_PER_SEC) / wdt->clk_freq;
return val;
}
void ar7240_gpio_config(void)
{
/* Disable clock obs
* clk_obs1(gpio13/bit8), clk_obs2(gpio14/bit9), clk_obs3(gpio15/bit10),
* clk_obs4(gpio16/bit11), clk_obs5(gpio17/bit12)
* clk_obs0(gpio1/bit19), 6(gpio11/bit20)
*/
ar7240_reg_wr (AR7240_GPIO_FUNC,
(ar7240_reg_rd(AR7240_GPIO_FUNC) & ~((0x1f<<8)|(0x3<<19))));
/* Enable eth Switch LEDs */
//ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) | (0x1f<<3)));
/* Clear AR7240_GPIO_FUNC BIT2 to ensure that software can control LED5(GPIO16) and LED6(GPIO17) */
ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & ~(0x1<<2)));
/* Set HORNET_BOOTSTRAP_STATUS BIT18 to ensure that software can control GPIO26 and GPIO27 */
//ar7240_reg_wr (HORNET_BOOTSTRAP_STATUS, (ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) | (0x1<<18)));
}
static void
ar7240_dispatch_pci_intr(struct pt_regs *regs)
{
#ifdef CONFIG_PERICOM
int pending;
pending = ar7240_reg_rd(AR7240_PCI_INT_STATUS) &
ar7240_reg_rd(AR7240_PCI_INT_MASK);
/* Don't do else-if. We have to service both interrupts */
if (pending & AR7240_PCI_INT_B_L) {
do_IRQ(AR7240_PCI_IRQ_DEV0, regs);
}
if (pending & AR7240_PCI_INT_C_L) {
do_IRQ(AR7240_PCI_IRQ_DEV1, regs);
}
#else
do_IRQ(AR7240_PCI_IRQ_DEV0, regs);
#endif /* CONFIG_PERICOM */
}
void led_toggle(void){
unsigned int gpio;
gpio = ar7240_reg_rd(AR7240_GPIO_OUT);
// SYS LED is connected to GPIO 14
gpio ^= 1 << 14;
ar7240_reg_wr(AR7240_GPIO_OUT, gpio);
}
static void
ar7240_dispatch_pci_intr(void)
{
#if 0
int pending;
pending = ar7240_reg_rd(AR7240_PCI_INT_STATUS) &
ar7240_reg_rd(AR7240_PCI_INT_MASK);
if (pending & PISR_DEV0)
do_IRQ(AR7240_PCI_IRQ_DEV0, regs);
else if (pending & PISR_DEV1)
do_IRQ(AR7240_PCI_IRQ_DEV1, regs);
else if (pending & PISR_DEV2)
do_IRQ(AR7240_PCI_IRQ_DEV2, regs);
#else
do_IRQ(AR7240_PCI_IRQ_DEV0);
#endif
}
void all_led_off(void){
unsigned int gpio;
gpio = ar7240_reg_rd(AR7240_GPIO_OUT);
// SYS LED (GPIO 14) and WLAN24 (GPIO 13)
SETBITVAL(gpio, 14, 1);
SETBITVAL(gpio, 13, 1);
ar7240_reg_wr(AR7240_GPIO_OUT, gpio);
}
void ar7240_gpio_setpin(unsigned int pin, unsigned int to)
{
//uint32_t r;
//r = ar7240_reg_rd(MBOX_INT_STATUS);
//ar7240_reg_rmw_clear(AR7240_GPIO_OE,(AR7240_LED_3|AR7240_LED_4|AR7240_LED_5));
unsigned long flags;
unsigned long dat;
if(to)
{
local_irq_save(flags);
//ar7240_reg_rmw_clear(AR7240_GPIO_OE,(AR7240_LED_3|AR7240_LED_4|AR7240_LED_5));
ar7240_reg_rmw_clear(AR7240_GPIO_OE,(IIS_CONTROL_CSB|IIS_CONTROL_SDIN|IIS_CONTROL_SCLK));
dat = ar7240_reg_rd(AR7240_GPIO_IN);
dat |= pin;
//ar7240_reg_wr(AR7240_GPIO_OE,(AR7240_LED_3|AR7240_LED_4|AR7240_LED_5));
ar7240_reg_wr(AR7240_GPIO_OE,(IIS_CONTROL_CSB|IIS_CONTROL_SDIN|IIS_CONTROL_SCLK));
ar7240_reg_wr(AR7240_GPIO_OUT,dat);
local_irq_restore(flags);
}
else
{
local_irq_save(flags);
//ar7240_reg_rmw_clear(AR7240_GPIO_OE,(AR7240_LED_3|AR7240_LED_4|AR7240_LED_5));
ar7240_reg_rmw_clear(AR7240_GPIO_OE,(IIS_CONTROL_CSB|IIS_CONTROL_SDIN|IIS_CONTROL_SCLK));
dat = ar7240_reg_rd(AR7240_GPIO_IN);
dat &= ~(pin);
//ar7240_reg_wr(AR7240_GPIO_OE,(AR7240_LED_3|AR7240_LED_4|AR7240_LED_5));
ar7240_reg_wr(AR7240_GPIO_OE,(IIS_CONTROL_CSB|IIS_CONTROL_SDIN|IIS_CONTROL_SCLK));
ar7240_reg_wr(AR7240_GPIO_OUT,dat);
local_irq_restore(flags);
}
}
int
ar7240_mem_config(void)
{
unsigned int tap_val1, tap_val2;
ar7240_ddr_initial_config(CFG_DDR_REFRESH_VAL);
/* Default tap values for starting the tap_init*/
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL0, 0x8);
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL1, 0x9);
ar7240_ddr_tap_init();
tap_val1 = ar7240_reg_rd(0xb800001c);
tap_val2 = ar7240_reg_rd(0xb8000020);
printf("#### TAP VALUE 1 = %x, 2 = %x\n",tap_val1, tap_val2);
ar7240_usb_initial_config();
ar7240_gpio_config();
return (ar7240_ddr_find_size());
}
void
ar7240_usb_otp_config(void)
{
unsigned int addr, reg_val, reg_usb;
int time_out, status, usb_valid;
for (addr = 0xb8114014; ;addr -= 0x10) {
status = 0;
time_out = 20;
reg_val = ar7240_reg_rd(addr);
while ((time_out > 0) && (~status)) {
if ((( ar7240_reg_rd(0xb8115f18)) & 0x7) == 0x4) {
status = 1;
} else {
status = 0;
}
time_out--;
}
reg_val = ar7240_reg_rd(0xb8115f1c);
if ((reg_val & 0x80) == 0x80){
usb_valid = 1;
reg_usb = reg_val & 0x000000ff;
}
if (addr == 0xb8114004) {
break;
}
}
if (usb_valid) {
reg_val = ar7240_reg_rd(0xb8116c88);
reg_val &= ~0x03f00000;
reg_val |= (reg_usb & 0xf) << 22;
ar7240_reg_wr(0xb8116c88, reg_val);
}
}
static int ar7240_pcibios_init(void)
{
if (is_ar9341()) {
return 0;
}
if (((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0) {
printf("***** Warning *****: PCIe WLAN H/W not found !!!\n");
return 0;
}
return 1;
}
void ath_set_tuning_caps(void)
{
typedef struct {
u_int8_t pad[0x28],
params_for_tuning_caps[2],
featureEnable;
} __attribute__((__packed__)) ar9300_eeprom_t;
ar9300_eeprom_t *eep;
uint32_t val;
#ifdef CONFIG_ATH_NAND_BR
eep = (ar9300_eeprom_t *)ath_get_nand_cal_data();
#else
eep = (ar9300_eeprom_t *)WLANCAL;
#endif /* CONFIG_ATH_NAND_BR */
val = 0;
/* checking feature enable bit 6 and caldata is valid */
if ((eep->featureEnable & 0x40) && (eep->pad[0x0] != 0xff)) {
/* xtal_capin -bit 17:23 and xtag_capout -bit 24:30*/
val = (eep->params_for_tuning_caps[0] & 0x7f) << 17;
val |= (eep->params_for_tuning_caps[0] & 0x7f) << 24;
} else {
/* default when no caldata available*/
/* checking clock in bit 4 */
if (ar7240_reg_rd(RST_BOOTSTRAP_ADDRESS) & 0x10) {
val = (0x1020 << 17); /*default 0x2040 for 40Mhz clock*/
} else {
val = (0x2040 << 17); /*default 0x4080 for 25Mhz clock*/
}
}
val |= (ar7240_reg_rd(XTAL_ADDRESS) & (((1 << 17) - 1) | (1 << 31)));
ar7240_reg_wr(XTAL_ADDRESS, val);
printf("Setting 0xb8116290 to 0x%x\n", val);
return;
}
int
wasp_mem_config(void)
{
unsigned int type, reg32;
type = wasp_ddr_initial_config(CFG_DDR_REFRESH_VAL);
/* Take WMAC out of reset */
reg32 = ar7240_reg_rd(AR7240_RESET);
reg32 = reg32 & ~AR7240_RESET_WMAC;
ar7240_reg_wr_nf(AR7240_RESET, reg32);
/* Switching regulator settings */
ar7240_reg_wr_nf(0x18116c40, 0x633c8176); /* AR_PHY_PMU1 */
#if !defined(CONFIG_ATH_NAND_BR)
if (ar7240_reg_rd(AR7240_REV_ID) & 0xf) {
if (type == 2) {
// ddr1
ar7240_reg_wr_nf(0x18116c44, 0x10000000); /* AR_PHY_PMU2 */
} else {
// ddr2 & sdram
ar7240_reg_wr_nf(0x18116c44, 0x10380000); /* AR_PHY_PMU2 */
}
} else {
ar7240_reg_wr_nf(0x18116c44, 0x10380000); /* AR_PHY_PMU2 */
}
#endif
wasp_usb_initial_config();
wasp_gpio_config();
reg32 = ar7240_ddr_find_size();
return reg32;
}
static void
read_id(void)
{
u32 rd = 0x777777;
ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS);
ar7240_spi_bit_banger(0x9f);
ar7240_spi_delay_8();
ar7240_spi_delay_8();
ar7240_spi_delay_8();
ar7240_spi_done();
/* rd = ar7240_reg_rd(AR7240_SPI_RD_STATUS); */
rd = ar7240_reg_rd(AR7240_SPI_READ);
printf("id read %#x\n", rd);
}
void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
CYG_ADDRWORD port;
cyg_uint8 _lcr;
cyg_uint32 freq;
hal_ar7240_sys_frequency();
freq = ar7240_ahb_freq;
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
port = ((channel_data_t*)__ch_data)->base;
/*
* undocumented. confirm, why write to GPIO for uart?
*/
ar7240_reg_wr(AR7240_GPIO_OE, 0xcff);
ar7240_reg_wr(AR7240_GPIO_OUT, 0x3b);
ar7240_reg_wr(AR7240_GPIO_FUNCTIONS, (ar7240_reg_rd(AR7240_GPIO_FUNCTIONS) | 0x48002));
ar7240_reg_wr(AR7240_GPIO_OUT, 0x2f);
// Disable port interrupts while changing hardware
HAL_WRITE_UINT32(port+SER_16550_IER, 0);
// Set databits, stopbits and parity.
_lcr = LCR_WL8 | LCR_SB1 | LCR_PN;
HAL_WRITE_UINT32(port+SER_16550_LCR, _lcr);
// Set baud rate.
cyg_hal_plf_serial_set_baud(port, freq / (16 *
CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD));
// Enable and clear FIFO
HAL_WRITE_UINT32(port+SER_16550_FCR, (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT));
#ifdef NOTANYMORE
// enable RTS to keep host side happy. Also allow interrupts
HAL_WRITE_UINT32( port+SER_16550_MCR, MCR_DTR | MCR_RTS | MCR_INT);
#endif
// Don't allow interrupts.
HAL_WRITE_UINT32(port+SER_16550_IER, 0);
}
/*
* Dispatch interrupts.
* XXX: This currently does not prioritize except in calling order. Eventually
* there should perhaps be a static map which defines, the IPs to be masked for
* a given IP.
*/
asmlinkage void plat_irq_dispatch(void)
{
int pending = read_c0_status() & read_c0_cause();
#if 0
if (!(pending & CAUSEF_IP7))
printk("%s: in irq dispatch \n", __func__);
#endif
if (pending & CAUSEF_IP7)
do_IRQ(AR7240_CPU_IRQ_TIMER);
else if (pending & CAUSEF_IP2) {
//printk("%s: 0x%x\n", __func__, ar7240_reg_rd(AR7240_PCIE_WMAC_INT_STATUS));
#ifdef CONFIG_WASP_SUPPORT
#ifdef CONFIG_PCI
if (unlikely(ar7240_reg_rd
(AR7240_PCIE_WMAC_INT_STATUS) & PCI_WMAC_INTR))
ar7240_dispatch_pci_intr();
else
#endif
do_IRQ(ATH_CPU_IRQ_WLAN);
#elif defined (CONFIG_MACH_HORNET)
do_IRQ(ATH_CPU_IRQ_WLAN);
#else
ar7240_dispatch_pci_intr();
#endif
}
else if (pending & CAUSEF_IP4)
do_IRQ(AR7240_CPU_IRQ_GE0);
else if (pending & CAUSEF_IP5)
do_IRQ(AR7240_CPU_IRQ_GE1);
else if (pending & CAUSEF_IP3)
do_IRQ(AR7240_CPU_IRQ_USB);
else if (pending & CAUSEF_IP6)
ar7240_dispatch_misc_intr();
/*
* Some PCI devices are write to clear. These writes are posted and might
* require a flush (r8169.c e.g.). Its unclear what will have more
* performance impact - flush after every interrupt or taking a few
* "spurious" interrupts. For now, its the latter.
*/
/*else
printk("spurious IRQ pending: 0x%x\n", pending);*/
}
irqreturn_t ar7240_i2s_intr(int irq, void *dev_id)
//irq_handler_t ar7240_i2s_intr(int irq, void *dev_id, struct pt_regs *regs)
{
uint32_t r;
//MBOX Rx DMA completion (one descriptor completed) interrupts
//
r = ar7240_reg_rd(MBOX_INT_STATUS);
if(r & RX_UNDERFLOW)
stats.rx_underflow++;
/* Ack the interrupts */
ar7240_reg_wr(MBOX_INT_STATUS, r);
return IRQ_HANDLED;
}
static void
ath_spi_read_id(void)
{
u32 rd = 0x777777;
ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS);
ar7240_spi_bit_banger(AR7240_SPI_CMD_RDID);
ar7240_spi_delay_8();
ar7240_spi_delay_8();
ar7240_spi_delay_8();
ar7240_spi_go();
rd = ar7240_reg_rd(AR7240_SPI_RD_STATUS);
printf("Flash Manuf Id 0x%x, DeviceId0 0x%x, DeviceId1 0x%x\n",
(rd >> 16) & 0xff, (rd >> 8) & 0xff, (rd >> 0) & 0xff);
}
void
wasp_usb_initial_config(void)
{
#define unset(a) (~(a))
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
ar7240_reg_wr_nf(AR934X_SWITCH_CLOCK_SPARE,
ar7240_reg_rd(AR934X_SWITCH_CLOCK_SPARE) |
SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(2));
} else {
ar7240_reg_wr_nf(AR934X_SWITCH_CLOCK_SPARE,
ar7240_reg_rd(AR934X_SWITCH_CLOCK_SPARE) |
SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(5));
}
udelay(1000);
ar7240_reg_wr(AR7240_RESET,
ar7240_reg_rd(AR7240_RESET) |
RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(1));
udelay(1000);
ar7240_reg_wr(AR7240_RESET,
ar7240_reg_rd(AR7240_RESET) &
unset(RST_RESET_USB_PHY_RESET_SET(1)));
udelay(1000);
ar7240_reg_wr(AR7240_RESET,
ar7240_reg_rd(AR7240_RESET) &
unset(RST_RESET_USB_PHY_ARESET_SET(1)));
udelay(1000);
ar7240_reg_wr(AR7240_RESET,
ar7240_reg_rd(AR7240_RESET) &
unset(RST_RESET_USB_HOST_RESET_SET(1)));
udelay(1000);
if ((ar7240_reg_rd(AR7240_REV_ID) & 0xf) == 0) {
/* Only for WASP 1.0 */
ar7240_reg_wr(0xb8116c84 ,
ar7240_reg_rd(0xb8116c84) & unset(1<<20));
}
}
void ar7240_all_led_on(void) {
unsigned int gpio;
gpio = ar7240_reg_rd(AR7240_GPIO_OUT);
#ifdef CONFIG_PID_MR302001
SETBITVAL(gpio, GPIO_WPS_LED_BIT, GPIO_WPS_LED_ON);
SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
SETBITVAL(gpio, GPIO_ETH_LED_BIT, GPIO_ETH_LED_ON);
#endif
#if defined(CONFIG_PID_WR70301) || defined(CONFIG_PID_WR720N03CH)
SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
#endif
#ifdef CONFIG_PID_MR304001
SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
SETBITVAL(gpio, GPIO_ETH_LED_BIT, GPIO_ETH_LED_ON);
#endif
#ifdef CONFIG_PID_MR10U01
SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
#endif
#if defined(CONFIG_PID_WR740N04) || defined(CONFIG_PID_MR322002)
SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON);
SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON);
SETBITVAL(gpio, GPIO_LAN1_LED_BIT, GPIO_LAN1_LED_ON);
SETBITVAL(gpio, GPIO_LAN2_LED_BIT, GPIO_LAN2_LED_ON);
SETBITVAL(gpio, GPIO_LAN3_LED_BIT, GPIO_LAN3_LED_ON);
SETBITVAL(gpio, GPIO_LAN4_LED_BIT, GPIO_LAN4_LED_ON);
SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON);
SETBITVAL(gpio, GPIO_QSS_LED_BIT, GPIO_QSS_LED_ON);
#ifdef CONFIG_PID_MR322002
SETBITVAL(gpio, GPIO_USB_LED_BIT, GPIO_USB_LED_ON);
#endif
#endif
ar7240_reg_wr(AR7240_GPIO_OUT, gpio);
}
int reset_button_status(void){
unsigned int gpio;
gpio = ar7240_reg_rd(AR7240_GPIO_IN);
if(gpio & (1 << GPIO_RST_BUTTON_BIT)){
#if defined(GPIO_RST_BUTTON_IS_ACTIVE_LOW)
return(0);
#else
return(1);
#endif
} else {
#if defined(GPIO_RST_BUTTON_IS_ACTIVE_LOW)
return(1);
#else
return(0);
#endif
}
}
/*
* Remove (clear) PLL and clock settings in FLASH
*/
int do_clear_clocks(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
unsigned char *data_pointer;
int i;
char buf[128];
unsigned int reg = 0;
// do we have PLL_MAGIC in FLASH?
reg = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET);
if(reg == PLL_IN_FLASH_MAGIC){
// backup entire block in which we store PLL/CLK settings
data_pointer = (unsigned char *)WEBFAILSAFE_UPLOAD_RAM_ADDRESS;
if(!data_pointer){
puts("## Error: couldn't allocate RAM for data block backup!\n");
return(1);
}
memcpy((void *)data_pointer, (void *)(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET), PLL_IN_FLASH_DATA_BLOCK_LENGTH);
// 16 bytes (4x 32-bit values)
for(i = 0; i < 16; i++){
data_pointer[PLL_IN_FLASH_MAGIC_OFFSET + i] = 0xFF;
}
// erase FLASH, copy data from RAM
sprintf(buf,
"erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX",
CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET,
PLL_IN_FLASH_DATA_BLOCK_LENGTH,
WEBFAILSAFE_UPLOAD_RAM_ADDRESS,
CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET,
PLL_IN_FLASH_DATA_BLOCK_LENGTH);
printf("Executing: %s\n\n", buf);
return(run_command(buf, 0));
} else {
puts("** Warning: there is no PLL and clocks configuration in FLASH!\n");
return(1);
}
}
/*
* Returns a string with memory type preceded by a space sign
*/
const char* print_mem_type(void){
unsigned int reg_val;
reg_val = (ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & HORNET_BOOTSTRAP_MEM_TYPE_MASK) >> HORNET_BOOTSTRAP_MEM_TYPE_SHIFT;
switch(reg_val){
case 0:
return " SDRAM";
break;
case 1:
return " DDR 16-bit";
break;
case 2:
return " DDR2 16-bit";
break;
default:
return "";
break;
}
}
static void ag7240_get_ethaddr(struct eth_device *dev)
{
unsigned char *eeprom;
unsigned char *mac = dev->enetaddr;
#ifndef CONFIG_AR7240_EMU
#ifdef CONFIG_ATH_NAND_BR
unsigned char sectorBuff[ATH_ETH_MAC_READ_SIZE];
eeprom = ath_eth_mac_addr(sectorBuff);
if(eeprom == NULL) {
/* mac address will be set to default mac address */
mac[0] = 0xff;
}
else {
#else /* CONFIG_ATH_NAND_BR */
eeprom = ag7240_mac_addr_loc();
#endif /* CONFIG_ATH_NAND_BR */
if (strcmp(dev->name, "eth0") == 0) {
memcpy(mac, eeprom, 6);
} else if (strcmp(dev->name, "eth1") == 0) {
eeprom += 6;
memcpy(mac, eeprom, 6);
} else {
printf("%s: unknown ethernet device %s\n", __func__, dev->name);
return;
}
#ifdef CONFIG_ATH_NAND_BR
}
#endif /* CONFIG_ATH_NAND_BR */
/* Use fixed address if the above address is invalid */
if (mac[0] != 0x00 || (mac[0] == 0xff && mac[5] == 0xff)) {
#else
if (1) {
#endif
mac[0] = 0x00;
mac[1] = 0x03;
mac[2] = 0x7f;
mac[3] = 0x09;
mac[4] = 0x0b;
mac[5] = 0xad;
printf("No valid address in Flash. Using fixed address\n");
} else {
printf("Fetching MAC Address from 0x%p\n", __func__, eeprom);
}
}
int ag7240_enet_initialize(bd_t * bis)
{
struct eth_device *dev[CFG_AG7240_NMACS];
u32 mask, mac_h, mac_l;
int i;
printf("ag934x_enet_initialize...\n");
if(is_ar933x() && (ar7240_reg_rd(AR7240_RESET)!=0))
ar7240_reg_wr(AR7240_RESET,0);
if(is_ar933x()) //Turn on LED
ar7240_reg_wr(AR7240_GPIO_BASE + 0x28 , ar7240_reg_rd(AR7240_GPIO_BASE + 0x28) | (0xF8));
for (i = 0; i < CFG_AG7240_NMACS; i++) {
if ((dev[i] = (struct eth_device *) malloc(sizeof (struct eth_device))) == NULL) {
puts("malloc failed\n");
return 0;
}
if ((ag7240_macs[i] = (ag7240_mac_t *) malloc(sizeof (ag7240_mac_t))) == NULL) {
puts("malloc failed\n");
return 0;
}
memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
memset(dev[i], 0, sizeof(dev[i]));
sprintf(dev[i]->name, "eth%d", i);
ag7240_get_ethaddr(dev[i]);
ag7240_macs[i]->mac_unit = i;
ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE ;
ag7240_macs[i]->dev = dev[i];
dev[i]->iobase = 0;
dev[i]->init = ag7240_clean_rx;
dev[i]->halt = ag7240_halt;
dev[i]->send = ag7240_send;
dev[i]->recv = ag7240_recv;
dev[i]->priv = (void *)ag7240_macs[i];
}
#if !defined(CONFIG_ATH_NAND_BR)
mask = AR7240_RESET_GE1_PHY;
ar7240_reg_rmw_set(AR7240_RESET, mask);
udelay(1000 * 100);
ar7240_reg_rmw_clear(AR7240_RESET, mask);
udelay(100);
#endif
mask = AR7240_RESET_GE0_PHY;
ar7240_reg_rmw_set(AR7240_RESET, mask);
udelay(1000 * 100);
ar7240_reg_rmw_clear(AR7240_RESET, mask);
udelay(100);
for (i = 0; i < CFG_AG7240_NMACS; i++) {
eth_register(dev[i]);
#if(CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);
#endif
ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST
| AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);
if(!i) {
mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE1_MAC);
if (is_ar7241() || is_ar7242() || is_wasp())
mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;
printf(" wasp reset mask:%x \n",mask);
ar7240_reg_rmw_set(AR7240_RESET, mask);
udelay(1000 * 100);
ar7240_reg_rmw_clear(AR7240_RESET, mask);
udelay(1000 * 100);
udelay(10 * 1000);
}
ag7240_mii_setup(ag7240_macs[i]);
/* if using header for register configuration, we have to */
/* configure s26 register after frame transmission is enabled */
if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */
#ifdef CONFIG_AR7242_S16_PHY
if (is_ar7242() || is_wasp()) {
athrs16_reg_init();
} else
#endif
{
#ifdef CONFIG_ATHRS17_PHY
athrs17_reg_init();
#endif
#ifdef CFG_ATHRS26_PHY
athrs26_reg_init();
#endif
#ifdef CFG_ATHRS27_PHY
printf("s27 reg init \n");
athrs27_reg_init();
#endif
#ifdef CONFIG_F1E_PHY
printf("F1Phy reg init \n");
athr_reg_init();
#endif
#ifdef CONFIG_VIR_PHY
printf("VIRPhy reg init \n");
athr_vir_reg_init();
#endif
#ifdef CONFIG_F2E_PHY
printf("F2Phy reg init \n");
athr_reg_init();
#endif
}
} else {
#ifdef CFG_ATHRS26_PHY
athrs26_reg_init_lan();
#endif
#ifdef CFG_ATHRS27_PHY
printf("s27 reg init lan \n");
athrs27_reg_init_lan();
#endif
}
ag7240_hw_start(ag7240_macs[i]);
ag7240_setup_fifos(ag7240_macs[i]);
udelay(100 * 1000);
{
unsigned char *mac = dev[i]->enetaddr;
printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name,
mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff,
mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
}
mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) |
(dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);
ag7240_phy_setup(ag7240_macs[i]->mac_unit);
printf("%s up\n",dev[i]->name);
}
return 1;
}
#if (CONFIG_COMMANDS & CFG_CMD_MII)
int
ag7240_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t *data)
{
ag7240_mac_t *mac = ag7240_name2mac(devname);
uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg, val;
volatile int rddata;
uint16_t ii = 0xFFFF;
/*
* Check for previous transactions are complete. Added to avoid
* race condition while running at higher frequencies.
*/
do
{
udelay(5);
rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
} while(rddata && --ii);
if (ii == 0)
printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);
ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);
ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr);
ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, AG7240_MGMT_CMD_READ);
do
{
udelay(5);
rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
} while(rddata && --ii);
if(ii==0)
printf("Error!!! Leave ag7240_miiphy_read without polling correct status!\n");
val = ag7240_reg_rd(mac, AG7240_MII_MGMT_STATUS);
ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);
if(data != NULL)
*data = val;
return val;
}
void ag7240_mii_setup(ag7240_mac_t *mac)
{
u32 mgmt_cfg_val;
u32 cpu_freq,ddr_freq,ahb_freq;
u32 check_cnt,revid_val;
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
#ifndef CFG_DUAL_PHY_SUPPORT
ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x271);
#endif
} else {
ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x570);
}
#if defined(CONFIG_AR7242_S16_PHY) || defined(CONFIG_ATHRS17_PHY)
if (is_wasp() && mac->mac_unit == 0) {
#ifdef CONFIG_AR7242_S16_PHY
printf("WASP ----> S16 PHY *\n");
#else
printf("WASP ----> S17 PHY *\n");
#endif
mgmt_cfg_val = 4;
if(mac->mac_unit == 0)
ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
udelay(1000);
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#ifdef CFG_ATHRS27_PHY
if (is_wasp()) {
printf("WASP ----> S27 PHY \n");
mgmt_cfg_val = 2;
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#ifdef CONFIG_F2E_PHY
if (is_wasp()) {
printf("WASP ----> F2 PHY *\n");
ar7240_reg_wr(AG7240_ETH_CFG, (AG7240_ETH_CFG_RMII_MASTER_MODE | AG7240_ETH_CFG_RMII_GE0
| AG7240_ETH_CFG_RMII_HISPD_GE0));
mgmt_cfg_val = 6;
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#if defined(CONFIG_F1E_PHY) || defined(CONFIG_VIR_PHY)
if (is_wasp()) {
#ifdef CONFIG_VIR_PHY
printf("WASP ----> VIR PHY *\n");
#else
printf("WASP ----> F1 PHY *\n");
#endif
if(mac->mac_unit == 0)
ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
mgmt_cfg_val = 6;
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
if ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) {
mgmt_cfg_val = 0x2;
if (mac->mac_unit == 0) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
}
else {
ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
switch (ahb_freq/1000000) {
case 150:
mgmt_cfg_val = 0x7;
break;
case 175:
mgmt_cfg_val = 0x5;
break;
case 200:
mgmt_cfg_val = 0x4;
break;
case 210:
mgmt_cfg_val = 0x9;
break;
case 220:
mgmt_cfg_val = 0x9;
break;
default:
mgmt_cfg_val = 0x7;
}
if ((is_ar7241() || is_ar7242())) {
/* External MII mode */
if (mac->mac_unit == 0 && is_ar7242()) {
mgmt_cfg_val = 0x6;
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
/* Virian */
mgmt_cfg_val = 0x4;
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
printf("Virian MDC CFG Value ==> %x\n",mgmt_cfg_val);
}
else if(is_ar933x()) {
//GE0 receives Rx/Tx clock, and use S26 phy
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE);
mgmt_cfg_val = 0xF;
if (mac->mac_unit == 1) {
check_cnt = 0;
while (check_cnt++ < 10) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
if(athrs26_mdc_check() == 0)
break;
#endif
}
if(check_cnt == 11)
printf("%s: MDC check failed\n", __func__);
}
}
else { /* Python 1.0 & 1.1 */
if (mac->mac_unit == 0) {
check_cnt = 0;
while (check_cnt++ < 10) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
if(athrs26_mdc_check() == 0)
break;
#endif
}
if(check_cnt == 11)
printf("%s: MDC check failed\n", __func__);
}
}
}
}
int ag7240_enet_initialize(bd_t * bis) {
struct eth_device *dev[CFG_AG7240_NMACS];
u32 mask, mac_h, mac_l;
int i;
#ifdef AG7240_DEBUG
printf("ag7240_enet_initialize...\n");
#endif
// TODO check this register!
ar7240_reg_wr(HORNET_BOOTSTRAP_STATUS, ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & ~HORNET_BOOTSTRAP_MDIO_SLAVE_MASK);
if (is_ar933x()) {
u32 rd = 0x0;
/*
* To get s26 out of reset, we have to...
* bit0~bit3: has to be deasserted
* bit4: has to be asserted
*/
rd = ar7240_reg_rd(AR7240_S26_CLK_CTRL_OFFSET) & ~(0x1f);
rd |= 0x10;
ar7240_reg_wr(AR7240_S26_CLK_CTRL_OFFSET, rd);
if (ar7240_reg_rd(AR7240_RESET) != 0) {
ar7240_reg_wr(AR7240_RESET, 0);
}
}
for (i = 0; i < CFG_AG7240_NMACS; i++) {
if ((dev[i] = (struct eth_device *) malloc(sizeof(struct eth_device))) == NULL) {
puts("## Error: malloc failed\n");
return 0;
}
if ((ag7240_macs[i] = (ag7240_mac_t *) malloc(sizeof(ag7240_mac_t))) == NULL) {
puts("## Error: malloc failed\n");
return 0;
}
memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
memset(dev[i], 0, sizeof(dev[i]));
sprintf(dev[i]->name, "eth%d", i);
ag7240_get_ethaddr(dev[i]);
ag7240_macs[i]->mac_unit = i;
ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE;
ag7240_macs[i]->dev = dev[i];
dev[i]->iobase = 0;
dev[i]->init = ag7240_clean_rx;
dev[i]->halt = ag7240_halt;
dev[i]->send = ag7240_send;
dev[i]->recv = ag7240_recv;
dev[i]->priv = (void *) ag7240_macs[i];
}
for (i = 0; i < CFG_AG7240_NMACS; i++) {
eth_register(dev[i]);
#if(CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);
#endif
ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);
if (!i) {
mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY);
if (is_ar7241() || is_ar7242() || is_wasp()){
mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;
}
ar7240_reg_rmw_set(AR7240_RESET, mask);
if (!is_ar933x()){
udelay(1000 * 100);
}
ar7240_reg_rmw_clear(AR7240_RESET, mask);
if (!is_ar933x()){
udelay(1000 * 100);
}
if (!is_ar933x()){
udelay(10 * 1000);
}
}
ag7240_hw_start(ag7240_macs[i]);
ag7240_setup_fifos(ag7240_macs[i]);
if (!is_ar933x()){
udelay(100 * 1000);
}
#ifdef AG7240_DEBUG
unsigned char *mac = dev[i]->enetaddr;
printf("\nInterface %s MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
#endif
mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);
/* if using header for register configuration, we have to */
/* configure s26 register after frame transmission is enabled */
if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */
#ifdef CONFIG_AR7242_S16_PHY
if (is_ar7242() || is_wasp()) {
athrs16_reg_init();
} else
#endif
{
#ifdef CFG_ATHRS26_PHY
#ifdef AG7240_DEBUG
printf("s26 reg init \n");
#endif
athrs26_reg_init();
#endif
#ifdef CFG_ATHRS27_PHY
#ifdef AG7240_DEBUG
printf("s27 reg init \n");
#endif
athrs27_reg_init();
#endif
#ifdef CONFIG_F1E_PHY
#ifdef AG7240_DEBUG
printf("F1Phy reg init \n");
#endif
athr_reg_init();
#endif
}
} else {
#ifdef CFG_ATHRS26_PHY
#ifdef AG7240_DEBUG
printf("athrs26_reg_init_lan\n");
#endif
athrs26_reg_init_lan();
#endif
#ifdef CFG_ATHRS27_PHY
#ifdef AG7240_DEBUG
printf("s27 reg init lan \n");
#endif
athrs27_reg_init_lan();
#endif
}
#ifdef AG7240_DEBUG
printf("ag7240_phy_setup\n");
#endif
//udelay(100*1000);
ag7240_phy_setup(ag7240_macs[i]->mac_unit);
#ifdef AG7240_DEBUG
printf("Interface %s is up\n", dev[i]->name);
#endif
}
return 1;
}
/*
* Called in ag7240_hw_start() function
* */
void ag7240_mii_setup(ag7240_mac_t *mac) {
u32 mgmt_cfg_val;
u32 cpu_freq, ddr_freq, ahb_freq;
u32 check_cnt;
#ifdef CFG_ATHRS27_PHY
if (is_wasp()) {
printf("WASP ----> S27 PHY \n");
mgmt_cfg_val = 2;
ar7240_reg_wr(0xb8050024, 0x271); // 25MHz ref clock
//ar7240_reg_wr(0xb8050024, 0x570); // 40MHz ref clock
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#ifdef CONFIG_AR7242_S16_PHY
if (is_wasp()) {
printf("WASP ----> S16 PHY *\n");
mgmt_cfg_val = 4;
if(mac->mac_unit == 0)
ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
ar7240_reg_rmw_clear(AG7240_ETH_SWITCH_CLK_SPARE, (1 << 6));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#ifdef CONFIG_F1E_PHY
if (is_wasp()) {
printf("WASP ----> F1 PHY *\n");
mgmt_cfg_val = 6;
if(mac->mac_unit == 0)
ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
if ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) {
mgmt_cfg_val = 0x2;
if (mac->mac_unit == 0) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
} else {
ar933x_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
switch (ahb_freq / 1000000) {
case 150:
mgmt_cfg_val = 0x7;
break;
case 175:
mgmt_cfg_val = 0x5;
break;
case 200:
mgmt_cfg_val = 0x4;
break;
case 210:
mgmt_cfg_val = 0x9;
break;
case 220:
mgmt_cfg_val = 0x9;
break;
default:
mgmt_cfg_val = 0x7;
}
if ((is_ar7241() || is_ar7242())) {
/* External MII mode */
if (mac->mac_unit == 0 && is_ar7242()) {
mgmt_cfg_val = 0x6;
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
/* Virian */
mgmt_cfg_val = 0x4;
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
printf("Virian MDC CFG Value ==> %x\n", mgmt_cfg_val);
} else if (is_ar933x()) {
//GE0 receives Rx/Tx clock, and use S26 phy
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE);
mgmt_cfg_val = 0xF;
if (mac->mac_unit == 1) {
check_cnt = 0;
while (check_cnt++ < 10) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
if (athrs26_mdc_check() == 0) {
break;
}
#endif
}
if (check_cnt == 11) {
printf("%s: MDC check failed\n", __func__);
}
}
} else { /* Python 1.0 & 1.1 */
if (mac->mac_unit == 0) {
check_cnt = 0;
while (check_cnt++ < 10) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
if (athrs26_mdc_check() == 0) {
break;
}
#endif
}
if (check_cnt == 11) {
printf("%s: MDC check failed\n", __func__);
}
}
}
}
}
void
ar7240_ddr_initial_config(uint32_t refresh)
{
int ddr2 = 0,ddr_config;
int ddr_config2,ext_mod,ddr2_ext_mod;
int mod_val,mod_val_init;
#ifndef COMPRESSED_UBOOT
printf("\nsri\n");
#endif
#if 0
ar7240_reg_wr(AR7240_RESET, AR7240_RESET_DDR);
udelay(10);
#endif
ddr2 = ((ar7240_reg_rd(0xb8050020) & 0x1) == 0);
#ifdef ENABLE_DYNAMIC_CONF
if(*(volatile int *)CFG_DDR_MAGIC_F == CFG_DDR_MAGIC){
ddr_config = CFG_DDR_CONFIG_VAL_F;
ddr_config2 = CFG_DDR_CONFIG2_VAL_F;
ext_mod = CFG_DDR_EXT_MODE_VAL_F;
ddr2_ext_mod = ext_mod;
}
else
#endif
{
#ifdef CONFIG_SUPPORT_AR7241
if (is_ar7241() || is_ar7242()) {
if (ddr2) {
#ifndef COMPRESSED_UBOOT
printf("%s(%d): virian ddr2 init\n", __func__, __LINE__);
#endif /* #ifndef COMPRESSED_UBOOT */
ddr_config = CFG_7241_DDR2_CONFIG_VAL;
ddr_config2 = CFG_7241_DDR2_CONFIG2_VAL;
#if defined(ENABLE_DYNAMIC_CONF) && (defined(CONFIG_WNR2200) || defined(CONFIG_WNR2000V3))
char *s;
s = getenv("ddr_ext_mode_value");
ext_mod = s?(int)simple_strtol(s,NULL,16):CFG_DDR_EXT_MODE_VAL;
#else
ext_mod = CFG_7241_DDR2_EXT_MODE_VAL;
#endif
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_7241_DDR2_MODE_VAL_INIT;
mod_val = CFG_7241_DDR2_MODE_VAL;
} else {
#ifndef COMPRESSED_UBOOT
printf("%s(%d): virian ddr1 init\n", __func__, __LINE__);
#endif /* #ifndef COMPRESSED_UBOOT */
ddr_config = CFG_7241_DDR1_CONFIG_VAL;
ddr_config2 = CFG_7241_DDR1_CONFIG2_VAL;
#if defined(ENABLE_DYNAMIC_CONF) && (defined(CONFIG_WNR2200) || defined(CONFIG_WNR2000V3))
char *s;
s = getenv("ddr_ext_mode_value");
ext_mod = s?(int)simple_strtol(s,NULL,16):CFG_DDR_EXT_MODE_VAL;
#else
ext_mod = CFG_7241_DDR1_EXT_MODE_VAL;
#endif
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_7241_DDR1_MODE_VAL_INIT;
mod_val = CFG_7241_DDR1_MODE_VAL;
}
}
else
#endif
{
#ifndef COMPRESSED_UBOOT
printf("%s(%d): python ddr init\n", __func__, __LINE__);
#endif /* #ifndef COMPRESSED_UBOOT */
ddr_config = CFG_DDR_CONFIG_VAL;
ddr_config2 = CFG_DDR_CONFIG2_VAL;
#if (defined(CONFIG_WNR1000V2) || defined(CONFIG_WNR1100) || defined(CONFIG_WNR612)) && defined(ENABLE_DYNAMIC_CONF)
char *s;
s = getenv("ddr_ext_mode_value");
ext_mod = s?(int)simple_strtol(s,NULL,16):CFG_DDR_EXT_MODE_VAL;
#else
ext_mod = CFG_DDR_EXT_MODE_VAL;
#endif
ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
mod_val_init = CFG_DDR_MODE_VAL_INIT;
mod_val = CFG_DDR_MODE_VAL;
}
}
if (ddr2) {
ar7240_reg_wr_nf(0xb800008c, 0xA59);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x10);
udelay(10);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x20);
udelay(10);
}
#if defined(CONFIG_WNR2200) || defined(CONFIG_WNR2000V3) || defined(CONFIG_AP121) || defined(CONFIG_WNR1000V4) || defined(CONFIG_HW29763847P16P64)
ar7240_reg_wr_nf(AR7240_DDR_CONFIG, ddr_config);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONFIG2, ddr_config2 | 0x80);
udelay(100);
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8);
udelay(10);
#else
else {
/*
* Set and store PLL configuration in FLASH
*/
int do_set_clocks(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){
unsigned int cpu_pll_config_flash, cpu_clock_control_flash, spi_control_flash, reg;
unsigned int ahb_freq, ddr_freq, cpu_freq, spi_freq;
unsigned int *data_pointer;
int i, index, profiles_count;
char buf[128];
profiles_count = sizeof(oc_profiles) / sizeof(ar9331_clock_profile);
// print all available profiles and current settings
if(argc == 1){
// read clocks
ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
// calculate SPI clock (we need to set bit 0 to 1 in SPI_FUNC_SELECT to access SPI registers)
ar7240_reg_wr(AR7240_SPI_FS, 0x01);
spi_freq = ahb_freq / (((ar7240_reg_rd(AR7240_SPI_CLOCK) & 0x3F) + 1) * 2);
ar7240_reg_wr(AR7240_SPI_FS, 0x0);
// make MHz from Hz
cpu_freq /= 1000000;
ddr_freq /= 1000000;
ahb_freq /= 1000000;
spi_freq /= 1000000;
printf("Current clocks (approximated):\n- CPU: %3d MHz\n", cpu_freq);
printf("- RAM: %3d MHz\n", ddr_freq);
printf("- AHB: %3d MHz\n", ahb_freq);
printf("- SPI: %3d MHz\n", spi_freq);
// reference clock
if(ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & HORNET_BOOTSTRAP_SEL_25M_40M_MASK){
puts("- REF: 40 MHz\n\n");
} else {
puts("- REF: 25 MHz\n\n");
}
// do we have PLL_MAGIC in FLASH?
reg = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET);
// read all register values stored in FLASH
cpu_pll_config_flash = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET + 4);
cpu_clock_control_flash = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET + 8);
spi_control_flash = ar7240_reg_rd(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET + 12);
printf("Available PLL and clocks configurations: %d\n\n", profiles_count);
puts(" | CPU | RAM | AHB | SPI | [ ]\n ---------------------------------\n");
for(i = 0; i < profiles_count; i++){
printf("%4d. |%4d |%4d |%4d |%4d | ", i + 1,
oc_profiles[i].cpu_clock,
oc_profiles[i].ram_clock,
oc_profiles[i].ahb_clock,
oc_profiles[i].spi_clock);
if(reg == PLL_IN_FLASH_MAGIC &&
oc_profiles[i].cpu_pll_config == cpu_pll_config_flash &&
oc_profiles[i].cpu_clk_control == cpu_clock_control_flash &&
oc_profiles[i].spi_control == spi_control_flash){
puts("[*]\n");
} else {
puts("[ ]\n");
}
}
puts("\n[*] = currently selected profile (stored in FLASH).\nAll clocks in MHz, run 'setclk X' to choose one.\n\n");
puts("** Notice:\n you should always make a backup of your device\n entire FLASH content before making any changes\n\n");
return(0);
} else {
// selected index
index = simple_strtoul(argv[1], NULL, 10);
if(index > profiles_count || index < 1){
printf("## Error: selected index should be in range 1..%d!\n", profiles_count);
return(1);
}
printf("You have selected profile: %d.\n\n", index);
// array is zero-based indexing
index--;
// backup entire block in which we store PLL/CLK settings
data_pointer = (unsigned int *)WEBFAILSAFE_UPLOAD_RAM_ADDRESS;
if(!data_pointer){
puts("## Error: couldn't allocate RAM for data block backup!\n");
return(1);
}
memcpy((void *)data_pointer, (void *)(CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET), PLL_IN_FLASH_DATA_BLOCK_LENGTH);
// save PLL_IN_FLASH_MAGIC and PLL/clocks registers values
data_pointer = (unsigned int *)(WEBFAILSAFE_UPLOAD_RAM_ADDRESS + PLL_IN_FLASH_MAGIC_OFFSET);
*data_pointer = PLL_IN_FLASH_MAGIC;
data_pointer++;
*data_pointer = oc_profiles[index].cpu_pll_config;
data_pointer++;
*data_pointer = oc_profiles[index].cpu_clk_control;
data_pointer++;
*data_pointer = oc_profiles[index].spi_control;
// erase FLASH, copy data from RAM
sprintf(buf,
"erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX",
CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET,
PLL_IN_FLASH_DATA_BLOCK_LENGTH,
WEBFAILSAFE_UPLOAD_RAM_ADDRESS,
CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET,
PLL_IN_FLASH_DATA_BLOCK_LENGTH);
printf("Executing: %s\n\n", buf);
return(run_command(buf, 0));
}
}
