/* poll current target status */
static int arm11_poll(struct target *target)
{
int retval;
struct arm11_common *arm11 = target_to_arm11(target);
CHECK_RETVAL(arm11_check_init(arm11));
if (arm11->dscr & DSCR_CORE_HALTED) {
if (target->state != TARGET_HALTED) {
enum target_state old_state = target->state;
LOG_DEBUG("enter TARGET_HALTED");
retval = arm11_debug_entry(arm11);
if (retval != ERROR_OK)
return retval;
target_call_event_callbacks(target,
(old_state == TARGET_DEBUG_RUNNING)
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED);
}
} else {
if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) {
LOG_DEBUG("enter TARGET_RUNNING");
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
}
}
return ERROR_OK;
}
/* talk to the target and set things up */
static int arm11_examine(struct target *target)
{
int retval;
char *type;
struct arm11_common *arm11 = target_to_arm11(target);
uint32_t didr, device_id;
uint8_t implementor;
/* FIXME split into do-first-time and do-every-time logic ... */
/* check IDCODE */
arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
struct scan_field idcode_field;
arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &idcode_field, TAP_DRPAUSE);
/* check DIDR */
arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
struct scan_field chain0_fields[2];
arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
/* assume the manufacturer id is ok; check the part # */
switch ((device_id >> 12) & 0xFFFF)
{
case 0x7B36:
type = "ARM1136";
break;
case 0x7B37:
type = "ARM11 MPCore";
break;
case 0x7B56:
type = "ARM1156";
break;
case 0x7B76:
arm11->arm.core_type = ARM_MODE_MON;
/* NOTE: could default arm11->hardware_step to true */
type = "ARM1176";
break;
default:
LOG_ERROR("unexpected ARM11 ID code");
return ERROR_FAIL;
}
LOG_INFO("found %s", type);
/* unlikely this could ever fail, but ... */
switch ((didr >> 16) & 0x0F) {
case ARM11_DEBUG_V6:
case ARM11_DEBUG_V61: /* supports security extensions */
break;
default:
LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
return ERROR_FAIL;
}
arm11->brp = ((didr >> 24) & 0x0F) + 1;
/** \todo TODO: reserve one brp slot if we allow breakpoints during step */
arm11->free_brps = arm11->brp;
LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
device_id, implementor, didr);
/* as a side-effect this reads DSCR and thus
* clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
* as suggested by the spec.
*/
retval = arm11_check_init(arm11);
if (retval != ERROR_OK)
return retval;
/* Build register cache "late", after target_init(), since we
* want to know if this core supports Secure Monitor mode.
*/
if (!target_was_examined(target))
CHECK_RETVAL(arm11_dpm_init(arm11, didr));
/* ETM on ARM11 still uses original scanchain 6 access mode */
if (arm11->arm.etm && !target_was_examined(target)) {
*register_get_last_cache_p(&target->reg_cache) =
etm_build_reg_cache(target, &arm11->jtag_info,
arm11->arm.etm);
CHECK_RETVAL(etm_setup(target));
}
target_set_examined(target);
return ERROR_OK;
}