void mmu_set_cpu_async_mode(void) { uint32_t reg; reg = arm_cp15_get_control(); reg |= 0xc0000000; arm_cp15_set_control(reg); }
BSP_START_TEXT_SECTION void bsp_memory_management_initialize(void) { uint32_t ctrl = arm_cp15_get_control(); arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache( ctrl, (uint32_t *) bsp_translation_table_base, ARM_MMU_DEFAULT_CLIENT_DOMAIN, &bsp_mm_config_table[0], bsp_mm_config_table_size ); }
static void BSP_START_SECTION lpc32xx_mmu_and_cache_setup(void) { uint32_t ctrl = 0; /* Disable MMU and cache, basic settings */ ctrl = arm_cp15_get_control(); ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_R | ARM_CP15_CTRL_C | ARM_CP15_CTRL_V | ARM_CP15_CTRL_M); ctrl |= ARM_CP15_CTRL_S | ARM_CP15_CTRL_A; arm_cp15_set_control(ctrl); arm_cp15_cache_invalidate(); arm_cp15_tlb_invalidate(); #ifndef LPC32XX_DISABLE_MMU lpc32xx_setup_translation_table_and_enable_mmu(ctrl); #endif }
void BSP_START_TEXT_SECTION bsp_start_hook_0(void) { uint32_t sctlr_val; sctlr_val = arm_cp15_get_control(); /* * Current U-boot loader seems to start kernel image * with I and D caches on and MMU enabled. * If RTEMS application image finds that cache is on * during startup then disable caches. */ if (sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) { if (sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) { /* * If the data cache is on then ensure that it is clean * before switching off to be extra carefull. */ arm_cp15_drain_write_buffer(); arm_cp15_data_cache_clean_and_invalidate(); } arm_cp15_flush_prefetch_buffer(); sctlr_val &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | ARM_CP15_CTRL_A); arm_cp15_set_control(sctlr_val); arm_cp15_tlb_invalidate(); arm_cp15_flush_prefetch_buffer(); arm_cp15_data_cache_invalidate(); arm_cp15_instruction_cache_invalidate(); } /* Clear Translation Table Base Control Register */ arm_cp15_set_translation_table_base_control_register(0); /* Clear Secure or Non-secure Vector Base Address Register */ arm_cp15_set_vector_base_address(0); }