void imx_init(u32 base, u32 baudrate, u32 input_clock)
{
unsigned int temp;
/* First, disable everything */
arm_writew(0x0, (void*)(base + UCR1));
arm_writew(0x0, (void*)(base + UCR2));
/*
* Set baud rate
*
* (UBMR + 1) / (UBIR + 1) = input_clock / (16 * BAUD_RATE)
* Set UBIR = 0xF:
* UBMR + 1 = input_clock / BAUD_RATE
*/
temp = arm_udiv32(input_clock, baudrate);
arm_writew(0xF, (void*)(base + UBIR));
arm_writew(temp - 1, (void*)(base + UBMR));
/* Set the UART to be 8 bits, 1 stop bit,
* no parity, fifo enabled */
arm_writel(UCR2_WS | UCR2_TXEN | UCR2_RXEN, (void*)(base + UCR2));
/* Finally, enable the UART */
arm_writew(UCR1_UARTEN, (void*)(base + UCR1));
}
void arm_timer_disable(void)
{
u32 ctrl;
ctrl = arm_readl((void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
ctrl &= ~TIMER_CTRL_ENABLE;
arm_writel(ctrl, (void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_CTRL));
}
void arm_timer_disable(void)
{
u32 ctrl;
ctrl = arm_readl((void *)(VERSATILE_TIMER0_1_BASE + TIMER_CTRL));
ctrl &= ~TIMER_CTRL_ENABLE;
arm_writel(ctrl, (void *)(VERSATILE_TIMER0_1_BASE + TIMER_CTRL));
}
void arm_timer_disable(void)
{
u32 ctrl;
ctrl = arm_readl((void *)(V2M_TIMER0 + TIMER_CTRL));
ctrl &= ~TIMER_CTRL_ENABLE;
arm_writel(ctrl, (void *)(V2M_TIMER0 + TIMER_CTRL));
}
void sp804_disable(void)
{
u32 ctrl;
ctrl = arm_readl((void *)(sp804_base + TIMER_CTRL));
ctrl &= ~TIMER_CTRL_ENABLE;
arm_writel(ctrl, (void *)(sp804_base + TIMER_CTRL));
}
void virtio_console_printch(physical_addr_t base, char ch)
{
u32 tmp;
struct virtio_console_config *p = (void *)base + VIRTIO_MMIO_CONFIG;
tmp = arm_readl((void *)(base + VIRTIO_MMIO_DEVICE_ID));
if (tmp != VIRTIO_ID_CONSOLE) {
return;
}
tmp = arm_readl((void *)(base + VIRTIO_MMIO_HOST_FEATURES));
if (!(tmp & (1 << VIRTIO_CONSOLE_F_EMERG_WRITE))) {
return;
}
arm_writel(ch, &p->emerg_wr);
}
int arm_board_timer_init(u32 usecs)
{
u32 val, irq;
u64 counter_mult, counter_shift, counter_mask;
counter_mask = 0xFFFFFFFFULL;
counter_shift = 20;
counter_mult = ((u64)1000000) << counter_shift;
counter_mult += (((u64)1000) >> 1);
counter_mult = arm_udiv64(counter_mult, ((u64)1000));
irq = IRQ_V2M_TIMER0;
val = arm_readl((void *)V2M_SYSCTL) | SCCTRL_TIMEREN0SEL_TIMCLK;
arm_writel(val, (void *)V2M_SYSCTL);
return sp804_init(usecs, V2M_TIMER0, irq,
counter_mask, counter_mult, counter_shift);
}
void arm_timer_clearirq(void)
{
arm_writel(1, (void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_INTCLR));
}
void arm_timer_change_period(u32 usec)
{
arm_writel(usec, (void *)(REALVIEW_PBA8_TIMER0_1_BASE + TIMER_LOAD));
}
void arm_board_init(void)
{
/* Unlock Lockable reigsters */
arm_writel(VERSATILE_SYS_LOCKVAL,
(void *)(VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET));
}
void arm_board_reset(void)
{
arm_writel(0x101,
(void *)(VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET));
}
void arm_board_reset(void)
{
arm_writel(~0x0, (void *)(V2M_SYS_FLAGSCLR));
arm_writel(0x0, (void *)(V2M_SYS_FLAGSSET));
arm_writel(0xc0900000, (void *)(V2M_SYS_CFGCTRL));
}
void arm_timer_clearirq(void)
{
arm_writel(1, (void *)(VERSATILE_TIMER0_1_BASE + TIMER_INTCLR));
}
void arm_timer_change_period(u32 usec)
{
arm_writel(usec, (void *)(VERSATILE_TIMER0_1_BASE + TIMER_LOAD));
}
void arm_timer_clearirq(void)
{
arm_writel(1, (void *)(V2M_TIMER0 + TIMER_INTCLR));
}
void arm_timer_change_period(u32 usec)
{
arm_writel(usec, (void *)(V2M_TIMER0 + TIMER_LOAD));
}
void sp804_change_period(u32 usec)
{
arm_writel(usec, (void *)(sp804_base + TIMER_LOAD));
}
static inline void gic_write(u32 val, virtual_addr_t addr)
{
arm_writel(val, (void *)(addr));
}
