static void
ar8327_phy_fixup(struct arswitch_softc *sc, int phy)
{
if (bootverbose)
device_printf(sc->sc_dev,
"%s: called; phy=%d; chiprev=%d\n", __func__,
phy,
sc->chip_rev);
switch (sc->chip_rev) {
case 1:
/* For 100M waveform */
arswitch_writedbg(sc->sc_dev, phy, 0, 0x02ea);
/* Turn on Gigabit clock */
arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x68a0);
break;
case 2:
arswitch_writemmd(sc->sc_dev, phy, 0x7, 0x3c);
arswitch_writemmd(sc->sc_dev, phy, 0x4007, 0x0);
/* fallthrough */
case 4:
arswitch_writemmd(sc->sc_dev, phy, 0x3, 0x800d);
arswitch_writemmd(sc->sc_dev, phy, 0x4003, 0x803f);
arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x6860);
arswitch_writedbg(sc->sc_dev, phy, 0x5, 0x2c46);
arswitch_writedbg(sc->sc_dev, phy, 0x3c, 0x6000);
break;
}
}
static void
ar8327_phy_fixup(struct arswitch_softc *sc, int phy)
{
switch (sc->chip_rev) {
case 1:
/* For 100M waveform */
arswitch_writedbg(sc->sc_dev, phy, 0, 0x02ea);
/* Turn on Gigabit clock */
arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x68a0);
break;
case 2:
arswitch_writemmd(sc->sc_dev, phy, 0x7, 0x3c);
arswitch_writemmd(sc->sc_dev, phy, 0x4007, 0x0);
/* fallthrough */
case 4:
arswitch_writemmd(sc->sc_dev, phy, 0x3, 0x800d);
arswitch_writemmd(sc->sc_dev, phy, 0x4003, 0x803f);
arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x6860);
arswitch_writedbg(sc->sc_dev, phy, 0x5, 0x2c46);
arswitch_writedbg(sc->sc_dev, phy, 0x3c, 0x6000);
break;
}
}
/*
* AR8316 specific functions
*/
static int
ar8316_hw_setup(struct arswitch_softc *sc)
{
/*
* Configure the switch mode based on whether:
*
* + The switch port is GMII/RGMII;
* + Port 4 is either connected to the CPU or to the internal switch.
*/
if (sc->is_rgmii && sc->phy4cpu) {
arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE,
AR8X16_MODE_RGMII_PORT4_ISO);
device_printf(sc->sc_dev,
"%s: MAC port == RGMII, port 4 = dedicated PHY\n",
__func__);
} else if (sc->is_rgmii) {
arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE,
AR8X16_MODE_RGMII_PORT4_SWITCH);
device_printf(sc->sc_dev,
"%s: MAC port == RGMII, port 4 = switch port\n",
__func__);
} else if (sc->is_gmii) {
arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE,
AR8X16_MODE_GMII);
device_printf(sc->sc_dev, "%s: MAC port == GMII\n", __func__);
} else {
device_printf(sc->sc_dev, "%s: unknown switch PHY config\n",
__func__);
return (ENXIO);
}
DELAY(1000); /* 1ms wait for things to settle */
/*
* If port 4 is RGMII, force workaround
*/
if (sc->is_rgmii && sc->phy4cpu) {
device_printf(sc->sc_dev,
"%s: port 4 RGMII workaround\n",
__func__);
/* work around for phy4 rgmii mode */
arswitch_writedbg(sc->sc_dev, 4, 0x12, 0x480c);
/* rx delay */
arswitch_writedbg(sc->sc_dev, 4, 0x0, 0x824e);
/* tx delay */
arswitch_writedbg(sc->sc_dev, 4, 0x5, 0x3d47);
DELAY(1000); /* 1ms, again to let things settle */
}
return (0);
}
