static u32 ast_get_vram_info(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; u8 jreg; u32 vram_size; ast_open_key(ast); vram_size = AST_VIDMEM_DEFAULT_SIZE; jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff); switch (jreg & 3) { case 0: vram_size = AST_VIDMEM_SIZE_8M; break; case 1: vram_size = AST_VIDMEM_SIZE_16M; break; case 2: vram_size = AST_VIDMEM_SIZE_32M; break; case 3: vram_size = AST_VIDMEM_SIZE_64M; break; } jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff); switch (jreg & 0x03) { case 1: vram_size -= 0x100000; break; case 2: vram_size -= 0x200000; break; case 3: vram_size -= 0x400000; break; } return vram_size; }
static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) { struct device_node *np = dev->pdev->dev.of_node; struct ast_private *ast = dev->dev_private; uint32_t data, jregd0, jregd1; /* Defaults */ ast->config_mode = ast_use_defaults; *scu_rev = 0xffffffff; /* Check if we have device-tree properties */ if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", scu_rev)) { /* We do, disable P2A access */ ast->config_mode = ast_use_dt; DRM_INFO("Using device-tree for configuration\n"); return; } /* Not all families have a P2A bridge */ if (dev->pdev->device != PCI_CHIP_AST2000) return; /* * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge * is disabled. We force using P2A if VGA only mode bit * is set D[7] */ jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { /* Double check it's actually working */ data = ast_read32(ast, 0xf004); if (data != 0xFFFFFFFF) { /* P2A works, grab silicon revision */ ast->config_mode = ast_use_p2a; DRM_INFO("Using P2A bridge for configuration\n"); /* Read SCU7c (silicon revision register) */ ast_write32(ast, 0xf004, 0x1e6e0000); ast_write32(ast, 0xf000, 0x1); *scu_rev = ast_read32(ast, 0x1207c); return; } } /* We have a P2A bridge but it's disabled */ DRM_INFO("P2A bridge disabled, using default configuration\n"); }
void ast_init_3rdtx(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; u8 jreg; u32 data; if (ast->chip == AST2300 || ast->chip == AST2400) { jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); switch (jreg & 0x0e) { case 0x04: ast_init_dvo(dev); break; case 0x08: ast_launch_m68k(dev); break; case 0x0c: ast_init_dvo(dev); break; default: if (ast->tx_chip_type == AST_TX_SIL164) ast_init_dvo(dev); else { ast_write32(ast, 0x12000, 0x1688a8a8); data = ast_read32(ast, 0x1202c); data &= 0xfffcffff; ast_write32(ast, 0, data); } } } }
static void send_nack(struct ast_private *ast) { u8 sendack; sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); sendack &= ~0x80; ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); }
void ast_init_3rdtx(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; u8 jreg; if (ast->chip == AST2300 || ast->chip == AST2400) { jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); switch (jreg & 0x0e) { case 0x04: ast_init_dvo(dev); break; case 0x08: ast_launch_m68k(dev); break; case 0x0c: ast_init_dvo(dev); break; default: if (ast->tx_chip_type == AST_TX_SIL164) ast_init_dvo(dev); else ast_init_analog(dev); } } }
static bool wait_fw_ready(struct ast_private *ast) { u8 waitready; u32 retry = 0; do { waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); waitready &= 0x40; udelay(100); } while ((!waitready) && (retry++ < 1000)); if (retry < 1000) return true; else return false; }
static bool wait_nack(struct ast_private *ast) { u8 waitack; u32 retry = 0; do { waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); waitack &= 0x80; udelay(100); } while ((waitack) && (retry++ < 1000)); if (retry < 1000) return true; else return false; }
static u32 ast_get_vram_info(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; u8 jreg; ast_open_key(ast); jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff); switch (jreg & 3) { case 0: return AST_VIDMEM_SIZE_8M; case 1: return AST_VIDMEM_SIZE_16M; case 2: return AST_VIDMEM_SIZE_32M; case 3: return AST_VIDMEM_SIZE_64M; } return AST_VIDMEM_DEFAULT_SIZE; }
uint32_t ast_get_max_dclk(struct drm_device *dev, int bpp) { struct ast_private *ast = dev->dev_private; uint32_t dclk, jreg; uint32_t dram_bus_width, mclk, dram_bandwidth, actual_dram_bandwidth, dram_efficency = 500; dram_bus_width = ast->dram_bus_width; mclk = ast->mclk; if (ast->chip == AST2100 || ast->chip == AST1100 || ast->chip == AST2200 || ast->chip == AST2150 || ast->dram_bus_width == 16) dram_efficency = 600; else if (ast->chip == AST2300) dram_efficency = 400; dram_bandwidth = mclk * dram_bus_width * 2 / 8; actual_dram_bandwidth = dram_bandwidth * dram_efficency / 1000; if (ast->chip == AST1180) dclk = actual_dram_bandwidth / ((bpp + 1) / 8); else { jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); if ((jreg & 0x08) && (ast->chip == AST2000)) dclk = actual_dram_bandwidth / ((bpp + 1 + 16) / 8); else if ((jreg & 0x08) && (bpp == 8)) dclk = actual_dram_bandwidth / ((bpp + 1 + 24) / 8); else dclk = actual_dram_bandwidth / ((bpp + 1) / 8); } if (ast->chip == AST2100 || ast->chip == AST2200 || ast->chip == AST2300 || ast->chip == AST1180) { if (dclk > 200) dclk = 200; } else { if (dclk > 165) dclk = 165; } return dclk; }
static bool ast_read_data(struct drm_device *dev, u8 *data) { struct ast_private *ast = dev->dev_private; u8 tmp; *data = 0; if (wait_ack(ast) == false) return false; tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff); *data = tmp; if (wait_nack(ast) == false) { send_nack(ast); return false; } send_nack(ast); return true; }
static int ast_detect_chip(struct drm_device *dev, bool *need_post) { struct ast_private *ast = dev->dev_private; uint32_t data, jreg; ast_open_key(ast); if (dev->pdev->device == PCI_CHIP_AST1180) { ast->chip = AST1100; DRM_INFO("AST 1180 detected\n"); } else { if (dev->pdev->revision >= 0x30) { ast->chip = AST2400; DRM_INFO("AST 2400 detected\n"); } else if (dev->pdev->revision >= 0x20) { ast->chip = AST2300; DRM_INFO("AST 2300 detected\n"); } else if (dev->pdev->revision >= 0x10) { uint32_t data; ast_write32(ast, 0xf004, 0x1e6e0000); ast_write32(ast, 0xf000, 0x1); data = ast_read32(ast, 0x1207c); switch (data & 0x0300) { case 0x0200: ast->chip = AST1100; DRM_INFO("AST 1100 detected\n"); break; case 0x0100: ast->chip = AST2200; DRM_INFO("AST 2200 detected\n"); break; case 0x0000: ast->chip = AST2150; DRM_INFO("AST 2150 detected\n"); break; default: ast->chip = AST2100; DRM_INFO("AST 2100 detected\n"); break; } ast->vga2_clone = false; } else { ast->chip = AST2000; DRM_INFO("AST 2000 detected\n"); } } /* * If VGA isn't enabled, we need to enable now or subsequent * access to the scratch registers will fail. We also inform * our caller that it needs to POST the chip * (Assumption: VGA not enabled -> need to POST) */ if (!ast_is_vga_enabled(dev)) { ast_enable_vga(dev); ast_enable_mmio(dev); DRM_INFO("VGA not enabled on entry, requesting chip POST\n"); *need_post = true; } else *need_post = false; /* Check if we support wide screen */ switch (ast->chip) { case AST1180: ast->support_wide_screen = true; break; case AST2000: ast->support_wide_screen = false; break; default: jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); if (!(jreg & 0x80)) ast->support_wide_screen = true; else if (jreg & 0x01) ast->support_wide_screen = true; else { ast->support_wide_screen = false; /* Read SCU7c (silicon revision register) */ ast_write32(ast, 0xf004, 0x1e6e0000); ast_write32(ast, 0xf000, 0x1); data = ast_read32(ast, 0x1207c); data &= 0x300; if (ast->chip == AST2300 && data == 0x0) /* ast1300 */ ast->support_wide_screen = true; if (ast->chip == AST2400 && data == 0x100) /* ast1400 */ ast->support_wide_screen = true; } break; } /* Check 3rd Tx option (digital output afaik) */ ast->tx_chip_type = AST_TX_NONE; /* * VGACRA3 Enhanced Color Mode Register, check if DVO is already * enabled, in that case, assume we have a SIL164 TMDS transmitter * * Don't make that assumption if we the chip wasn't enabled and * is at power-on reset, otherwise we'll incorrectly "detect" a * SIL164 when there is none. */ if (!*need_post) { jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); if (jreg & 0x80) ast->tx_chip_type = AST_TX_SIL164; } if ((ast->chip == AST2300) || (ast->chip == AST2400)) { /* * On AST2300 and 2400, look the configuration set by the SoC in * the SOC scratch register #1 bits 11:8 (interestingly marked * as "reserved" in the spec) */ jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); switch (jreg) { case 0x04: ast->tx_chip_type = AST_TX_SIL164; break; case 0x08: ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL); if (ast->dp501_fw_addr) { /* backup firmware */ if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) { kfree(ast->dp501_fw_addr); ast->dp501_fw_addr = NULL; } } /* fallthrough */ case 0x0c: ast->tx_chip_type = AST_TX_DP501; } } /* Print stuff for diagnostic purposes */ switch(ast->tx_chip_type) { case AST_TX_SIL164: DRM_INFO("Using Sil164 TMDS transmitter\n"); break; case AST_TX_DP501: DRM_INFO("Using DP501 DisplayPort transmitter\n"); break; default: DRM_INFO("Analog VGA only\n"); } return 0; }
static int ast_detect_chip(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; uint32_t data, jreg; if (dev->pdev->device == PCI_CHIP_AST1180) { ast->chip = AST1100; DRM_INFO("AST 1180 detected\n"); } else { if (dev->pdev->revision >= 0x30) { ast->chip = AST2400; DRM_INFO("AST 2400 detected\n"); } else if (dev->pdev->revision >= 0x20) { ast->chip = AST2300; DRM_INFO("AST 2300 detected\n"); } else if (dev->pdev->revision >= 0x10) { uint32_t data; ast_write32(ast, 0xf004, 0x1e6e0000); ast_write32(ast, 0xf000, 0x1); data = ast_read32(ast, 0x1207c); switch (data & 0x0300) { case 0x0200: ast->chip = AST1100; DRM_INFO("AST 1100 detected\n"); break; case 0x0100: ast->chip = AST2200; DRM_INFO("AST 2200 detected\n"); break; case 0x0000: ast->chip = AST2150; DRM_INFO("AST 2150 detected\n"); break; default: ast->chip = AST2100; DRM_INFO("AST 2100 detected\n"); break; } ast->vga2_clone = false; } else { ast->chip = AST2000; DRM_INFO("AST 2000 detected\n"); } } switch (ast->chip) { case AST1180: ast->support_wide_screen = true; break; case AST2000: ast->support_wide_screen = false; break; default: jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); if (!(jreg & 0x80)) ast->support_wide_screen = true; else if (jreg & 0x01) ast->support_wide_screen = true; else { ast->support_wide_screen = false; ast_write32(ast, 0xf004, 0x1e6e0000); ast_write32(ast, 0xf000, 0x1); data = ast_read32(ast, 0x1207c); data &= 0x300; if (ast->chip == AST2300 && data == 0x0) /* ast1300 */ ast->support_wide_screen = true; if (ast->chip == AST2400 && data == 0x100) /* ast1400 */ ast->support_wide_screen = true; } break; } ast->tx_chip_type = AST_TX_NONE; jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); if (jreg & 0x80) ast->tx_chip_type = AST_TX_SIL164; if ((ast->chip == AST2300) || (ast->chip == AST2400)) { jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); switch (jreg) { case 0x04: ast->tx_chip_type = AST_TX_SIL164; break; case 0x08: ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL); if (ast->dp501_fw_addr) { /* backup firmware */ if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) { kfree(ast->dp501_fw_addr); ast->dp501_fw_addr = NULL; } } /* fallthrough */ case 0x0c: ast->tx_chip_type = AST_TX_DP501; } } return 0; }
static bool ast_init_dvo(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; u8 jreg; u32 data; ast_write32(ast, 0xf004, 0x1e6e0000); ast_write32(ast, 0xf000, 0x1); ast_write32(ast, 0x12000, 0x1688a8a8); jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); if (!(jreg & 0x80)) { /* Init SCU DVO Settings */ data = ast_read32(ast, 0x12008); /* delay phase */ data &= 0xfffff8ff; data |= 0x00000500; ast_write32(ast, 0x12008, data); if (ast->chip == AST2300) { data = ast_read32(ast, 0x12084); /* multi-pins for DVO single-edge */ data |= 0xfffe0000; ast_write32(ast, 0x12084, data); data = ast_read32(ast, 0x12088); /* multi-pins for DVO single-edge */ data |= 0x000fffff; ast_write32(ast, 0x12088, data); data = ast_read32(ast, 0x12090); /* multi-pins for DVO single-edge */ data &= 0xffffffcf; data |= 0x00000020; ast_write32(ast, 0x12090, data); } else { /* AST2400 */ data = ast_read32(ast, 0x12088); /* multi-pins for DVO single-edge */ data |= 0x30000000; ast_write32(ast, 0x12088, data); data = ast_read32(ast, 0x1208c); /* multi-pins for DVO single-edge */ data |= 0x000000cf; ast_write32(ast, 0x1208c, data); data = ast_read32(ast, 0x120a4); /* multi-pins for DVO single-edge */ data |= 0xffff0000; ast_write32(ast, 0x120a4, data); data = ast_read32(ast, 0x120a8); /* multi-pins for DVO single-edge */ data |= 0x0000000f; ast_write32(ast, 0x120a8, data); data = ast_read32(ast, 0x12094); /* multi-pins for DVO single-edge */ data |= 0x00000002; ast_write32(ast, 0x12094, data); } } /* Force to DVO */ data = ast_read32(ast, 0x1202c); data &= 0xfffbffff; ast_write32(ast, 0x1202c, data); /* Init VGA DVO Settings */ ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); return true; }
bool ast_launch_m68k(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; u32 i, data, len = 0; u32 boot_address; u8 *fw_addr = NULL; u8 jreg; data = ast_mindwm(ast, 0x1e6e2100) & 0x01; if (!data) { if (ast->dp501_fw_addr) { fw_addr = ast->dp501_fw_addr; len = 32*1024; } else if (ast->dp501_fw) { fw_addr = (u8 *)ast->dp501_fw->data; len = ast->dp501_fw->size; } /* Get BootAddress */ ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8); data = ast_mindwm(ast, 0x1e6e0004); switch (data & 0x03) { case 0: boot_address = 0x44000000; break; default: case 1: boot_address = 0x48000000; break; case 2: boot_address = 0x50000000; break; case 3: boot_address = 0x60000000; break; } boot_address -= 0x200000; /* -2MB */ /* copy image to buffer */ for (i = 0; i < len; i += 4) { data = *(u32 *)(fw_addr + i); ast_moutdwm(ast, boot_address + i, data); } /* Init SCU */ ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8); /* Launch FW */ ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address); ast_moutdwm(ast, 0x1e6e2100, 1); /* Update Scratch */ data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff; /* D[11:9] = 100b: UEFI handling */ data |= 0x800; ast_moutdwm(ast, 0x1e6e2040, data); jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */ jreg |= 0x02; ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg); } return true; }