void mem_init(void)
{
struct atmel_mpddrc_config ddr2;
const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
u32 tmp;
ddr2_conf(&ddr2);
/* Enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
at91_system_clk_enable(AT91_PMC_DDR);
tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE;
writel(tmp, &mpddr->rd_data_path);
tmp = readl(&mpddr->io_calibr);
tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV |
ATMEL_MPDDRC_IO_CALIBR_TZQIO |
ATMEL_MPDDRC_IO_CALIBR_CALCODEP |
ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) |
ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 |
ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) |
ATMEL_MPDDRC_IO_CALIBR_EN_CALIB;
writel(tmp, &mpddr->io_calibr);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
}
void mem_init(void)
{
struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
struct atmel_mpddrc_config ddrc_config;
u32 reg;
ddrc_conf(&ddrc_config);
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
at91_system_clk_enable(AT91_PMC_SYS_CLK_DDRCK);
reg = readl(&mpddrc->io_calibr);
reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
writel(reg, &mpddrc->io_calibr);
writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
&mpddrc->rd_data_path);
ddr3_init(ATMEL_BASE_DDRCS, &ddrc_config);
writel(0x3, &mpddrc->cal_mr4);
writel(64, &mpddrc->tim_cal);
}
void mem_init(void)
{
struct atmel_mpddrc_config ddr2;
ddr2_conf(&ddr2);
at91_system_clk_enable(AT91_PMC_DDR);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
}
void mem_init(void)
{
struct atmel_mpddrc_config ddr2;
ddr2_conf(&ddr2);
/* Enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
at91_system_clk_enable(AT91_PMC_DDR);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
}
void mem_init(void)
{
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
struct atmel_mpddrc_config ddr2;
unsigned long csa;
ddr2_conf(&ddr2);
/* enable DDR2 clock */
at91_system_clk_enable(AT91_PMC_DDR);
/* Chip select 1 is for DDR2/SDRAM */
csa = readl(&matrix->ebicsa);
csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
writel(csa, &matrix->ebicsa);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
}