static int ata_ali_ch_attach(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); struct ata_channel *ch = device_get_softc(dev); /* setup the usual register normal pci style */ if (ata_pci_ch_attach(dev)) return ENXIO; if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) ch->flags |= ATA_CHECKS_CABLE; /* older chips can't do 48bit DMA transfers */ if (ctlr->chip->chiprev <= 0xc4) { ch->flags |= ATA_NO_48BIT_DMA; if (ch->dma.max_iosize > 256 * 512) ch->dma.max_iosize = 256 * 512; } #ifdef ATA_CAM if (ctlr->chip->cfg2 & ALI_NEW) ch->flags |= ATA_NO_ATAPI_DMA; #endif return 0; }
static int ata_national_ch_attach(device_t dev) { struct ata_channel *ch = device_get_softc(dev); ch->dma.alignment = 16; ch->dma.max_iosize = 64 * DEV_BSIZE; return (ata_pci_ch_attach(dev)); }
static int ata_via_ch_attach(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); struct ata_channel *ch = device_get_softc(dev); /* newer SATA chips has resources in one BAR for each channel */ if (ctlr->chip->cfg2 & VIABAR) { struct resource *r_io; int i, rid; ata_pci_dmainit(dev); rid = PCIR_BAR(ch->unit); if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), SYS_RES_IOPORT, &rid, RF_ACTIVE))) return ENXIO; for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { ch->r_io[i].res = r_io; ch->r_io[i].offset = i; } ch->r_io[ATA_CONTROL].res = r_io; ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; ch->r_io[ATA_IDX_ADDR].res = r_io; ata_default_registers(dev); for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { ch->r_io[i].res = ctlr->r_res1; ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); } ata_pci_hw(dev); if (ch->unit >= 2) return 0; } else { /* setup the usual register normal pci style */ if (ata_pci_ch_attach(dev)) return ENXIO; } ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); ch->r_io[ATA_SERROR].res = ctlr->r_res2; ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); ch->hw.status = ata_via_status; ch->flags |= ATA_NO_SLAVE; ch->flags |= ATA_SATA; ch->flags |= ATA_PERIODIC_POLL; ata_sata_scr_write(ch, -1, ATA_SERROR, 0xffffffff); return 0; }
static int ata_jmicron_ch_attach(device_t dev) { struct ata_channel *ch = device_get_softc(dev); int error; error = ata_pci_ch_attach(dev); ch->flags |= ATA_CHECKS_CABLE; return (error); }
static int ata_nvidia_ch_attach_dumb(device_t dev) { struct ata_channel *ch = device_get_softc(dev); if (ata_pci_ch_attach(dev)) return ENXIO; ch->flags |= ATA_SATA; return 0; }
static int ata_via_sata_ch_attach(device_t dev) { struct ata_channel *ch = device_get_softc(dev); if (ata_pci_ch_attach(dev)) return ENXIO; if (ch->unit == 0) ch->flags |= ATA_SATA; return (0); }
static int ata_via_ch_attach(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); struct ata_channel *ch = device_get_softc(dev); /* newer SATA chips has resources in one BAR for each channel */ if (ctlr->chip->cfg2 & VIABAR) { struct resource *r_io; int i, rid; ata_pci_dmainit(dev); rid = PCIR_BAR(ch->unit); if (!(r_io = bus_alloc_resource_any(device_get_parent(dev), SYS_RES_IOPORT, &rid, RF_ACTIVE))) return ENXIO; for (i = ATA_DATA; i <= ATA_COMMAND; i ++) { ch->r_io[i].res = r_io; ch->r_io[i].offset = i; } ch->r_io[ATA_CONTROL].res = r_io; ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE; ch->r_io[ATA_IDX_ADDR].res = r_io; ata_default_registers(dev); for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { ch->r_io[i].res = ctlr->r_res1; ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); } ata_pci_hw(dev); if (ch->unit >= 2) return 0; } else { /* setup the usual register normal pci style */ if (ata_pci_ch_attach(dev)) return ENXIO; } ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1); ch->r_io[ATA_SERROR].res = ctlr->r_res2; ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1); ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1); ch->flags |= ATA_NO_SLAVE; ch->flags |= ATA_SATA; /* XXX SOS PHY hotplug handling missing in VIA chip ?? */ /* XXX SOS unknown how to enable PHY state change interrupt */ return 0; }
static int ata_acard_ch_attach(device_t dev) { struct ata_channel *ch = device_get_softc(dev); /* setup the usual register normal pci style */ if (ata_pci_ch_attach(dev)) return ENXIO; ch->hw.status = ata_acard_status; ch->flags |= ATA_NO_ATAPI_DMA; return 0; }
static int ata_amd_ch_attach(device_t dev) { struct ata_pci_controller *ctlr; struct ata_channel *ch; int error; ctlr = device_get_softc(device_get_parent(dev)); ch = device_get_softc(dev); error = ata_pci_ch_attach(dev); if (ctlr->chip->cfg1 & AMD_CABLE) ch->flags |= ATA_CHECKS_CABLE; return (error); }
static int ata_netcell_ch_attach(device_t dev) { struct ata_channel *ch = device_get_softc(dev); /* setup the usual register normal pci style */ if (ata_pci_ch_attach(dev)) return ENXIO; /* the NetCell only supports 16 bit PIO transfers */ ch->flags |= ATA_USE_16BIT; return 0; }
static int ata_highpoint_ch_attach(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); struct ata_channel *ch = device_get_softc(dev); /* setup the usual register normal pci style */ if (ata_pci_ch_attach(dev)) return (ENXIO); ch->flags |= ATA_ALWAYS_DMASTAT; ch->flags |= ATA_CHECKS_CABLE; if (ctlr->chip->cfg1 == HPT_366) ch->flags |= ATA_NO_ATAPI_DMA; return (0); }
static int ata_cmd_ch_attach(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); struct ata_channel *ch = device_get_softc(dev); /* setup the usual register normal pci style */ if (ata_pci_ch_attach(dev)) return ENXIO; if (ctlr->chip->cfg2 & SII_INTR) ch->hw.status = ata_cmd_status; return 0; }
static int ata_via_sata_ch_attach(device_t dev) { struct ata_channel *ch = device_get_softc(dev); if (ata_pci_ch_attach(dev)) return ENXIO; if (ch->unit == 0) { ch->hw.status = ata_via_sata_status; ch->hw.pm_read = ata_via_sata_scr_read; ch->hw.pm_write = ata_via_sata_scr_write; ch->flags |= ATA_PERIODIC_POLL; ch->flags |= ATA_SATA; ata_sata_scr_write(ch, 0, ATA_SERROR, 0xffffffff); ata_sata_scr_write(ch, 1, ATA_SERROR, 0xffffffff); } return (0); }
static int ata_nvidia_ch_attach(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); struct ata_channel *ch = device_get_softc(dev); /* setup the usual register normal pci style */ if (ata_pci_ch_attach(dev)) return ENXIO; ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6); ch->r_io[ATA_SERROR].res = ctlr->r_res2; ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6); ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6); ch->hw.status = ata_nvidia_status; ch->flags |= ATA_NO_SLAVE; ch->flags |= ATA_SATA; return 0; }
static int ata_sis_ch_attach(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); struct ata_channel *ch = device_get_softc(dev); int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6); /* setup the usual register normal pci style */ if (ata_pci_ch_attach(dev)) return ENXIO; ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; ch->r_io[ATA_SSTATUS].offset = 0x00 + offset; ch->r_io[ATA_SERROR].res = ctlr->r_res2; ch->r_io[ATA_SERROR].offset = 0x04 + offset; ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; ch->r_io[ATA_SCONTROL].offset = 0x08 + offset; ch->flags |= ATA_NO_SLAVE; ch->flags |= ATA_SATA; /* XXX SOS PHY hotplug handling missing in SiS chip ?? */ /* XXX SOS unknown how to enable PHY state change interrupt */ return 0; }