static void ixp4xx_setup_port(struct ata_ioports *ioaddr, struct ixp4xx_pata_data *data) { ioaddr->cmd_addr = data->cs0; ioaddr->altstatus_addr = data->cs1 + 0x06; ioaddr->ctl_addr = data->cs1 + 0x06; ata_std_ports(ioaddr); #ifndef __ARMEB__ /* adjust the addresses to handle the address swizzling of the * ixp4xx in little endian mode. */ *(unsigned long *)&ioaddr->data_addr ^= 0x02; *(unsigned long *)&ioaddr->cmd_addr ^= 0x03; *(unsigned long *)&ioaddr->altstatus_addr ^= 0x03; *(unsigned long *)&ioaddr->ctl_addr ^= 0x03; *(unsigned long *)&ioaddr->error_addr ^= 0x03; *(unsigned long *)&ioaddr->feature_addr ^= 0x03; *(unsigned long *)&ioaddr->nsect_addr ^= 0x03; *(unsigned long *)&ioaddr->lbal_addr ^= 0x03; *(unsigned long *)&ioaddr->lbam_addr ^= 0x03; *(unsigned long *)&ioaddr->lbah_addr ^= 0x03; *(unsigned long *)&ioaddr->device_addr ^= 0x03; *(unsigned long *)&ioaddr->status_addr ^= 0x03; *(unsigned long *)&ioaddr->command_addr ^= 0x03; #endif }
static int isapnp_init_one(struct pnp_dev *idev, const struct pnp_device_id *dev_id) { struct ata_host *host; struct ata_port *ap; void __iomem *cmd_addr, *ctl_addr; int irq = 0; irq_handler_t handler = NULL; if (pnp_port_valid(idev, 0) == 0) return -ENODEV; if (pnp_irq_valid(idev, 0)) { irq = pnp_irq(idev, 0); handler = ata_interrupt; } /* allocate host */ host = ata_host_alloc(&idev->dev, 1); if (!host) return -ENOMEM; /* acquire resources and fill host */ cmd_addr = devm_ioport_map(&idev->dev, pnp_port_start(idev, 0), 8); if (!cmd_addr) return -ENOMEM; ap = host->ports[0]; ap->ops = &isapnp_port_ops; ap->pio_mask = 1; ap->flags |= ATA_FLAG_SLAVE_POSS; ap->ioaddr.cmd_addr = cmd_addr; if (pnp_port_valid(idev, 1) == 0) { ctl_addr = devm_ioport_map(&idev->dev, pnp_port_start(idev, 1), 1); ap->ioaddr.altstatus_addr = ctl_addr; ap->ioaddr.ctl_addr = ctl_addr; } ata_std_ports(&ap->ioaddr); ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", (unsigned long long)pnp_port_start(idev, 0), (unsigned long long)pnp_port_start(idev, 1)); /* activate */ return ata_host_activate(host, irq, handler, 0, &isapnp_sht); }
static void vt6421_init_addrs(struct ata_probe_ent *probe_ent, void __iomem * const *iomap, unsigned int port) { void __iomem *reg_addr = iomap[port]; void __iomem *bmdma_addr = iomap[4] + (port * 8); probe_ent->port[port].cmd_addr = reg_addr; probe_ent->port[port].altstatus_addr = probe_ent->port[port].ctl_addr = (void __iomem *) ((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS); probe_ent->port[port].bmdma_addr = bmdma_addr; probe_ent->port[port].scr_addr = vt6421_scr_addr(iomap[5], port); ata_std_ports(&probe_ent->port[port]); }
static void vt6421_init_addrs(struct ata_probe_ent *probe_ent, struct pci_dev *pdev, unsigned int port) { unsigned long reg_addr = pci_resource_start(pdev, port); unsigned long bmdma_addr = pci_resource_start(pdev, 4) + (port * 8); unsigned long scr_addr; probe_ent->port[port].cmd_addr = reg_addr; probe_ent->port[port].altstatus_addr = probe_ent->port[port].ctl_addr = (reg_addr + 8) | ATA_PCI_CTL_OFS; probe_ent->port[port].bmdma_addr = bmdma_addr; scr_addr = vt6421_scr_addr(pci_resource_start(pdev, 5), port); probe_ent->port[port].scr_addr = scr_addr; ata_std_ports(&probe_ent->port[port]); }
static void vt6421_init_addrs(struct ata_port *ap) { void __iomem * const * iomap = ap->host->iomap; void __iomem *reg_addr = iomap[ap->port_no]; void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8); struct ata_ioports *ioaddr = &ap->ioaddr; ioaddr->cmd_addr = reg_addr; ioaddr->altstatus_addr = ioaddr->ctl_addr = (void __iomem *) ((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS); ioaddr->bmdma_addr = bmdma_addr; ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no); ata_std_ports(ioaddr); ata_port_pbar_desc(ap, ap->port_no, -1, "port"); ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma"); }
static void rb500_pata_setup_ports(struct ata_host *ah) { struct rb500_cf_info *info = ah->private_data; struct ata_port *ap; ap = ah->ports[0]; ap->ops = &rb500_pata_port_ops; ap->pio_mask = 0x1f; /* PIO4 */ ap->flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO; ap->ioaddr.cmd_addr = info->iobase + RB500_CF_REG_CMD; ap->ioaddr.ctl_addr = info->iobase + RB500_CF_REG_CTRL; ap->ioaddr.altstatus_addr = info->iobase + RB500_CF_REG_CTRL; ata_std_ports(&ap->ioaddr); ap->ioaddr.data_addr = info->iobase + RB500_CF_REG_DATA; }
static void ixp4xx_setup_port(struct ata_port *ap, struct ixp4xx_pata_data *data, unsigned long raw_cs0, unsigned long raw_cs1) { struct ata_ioports *ioaddr = &ap->ioaddr; unsigned long raw_cmd = raw_cs0; unsigned long raw_ctl = raw_cs1 + 0x06; ioaddr->cmd_addr = data->cs0; ioaddr->altstatus_addr = data->cs1 + 0x06; ioaddr->ctl_addr = data->cs1 + 0x06; ata_std_ports(ioaddr); #ifndef __ARMEB__ /* adjust the addresses to handle the address swizzling of the * ixp4xx in little endian mode. */ *(unsigned long *)&ioaddr->data_addr ^= 0x02; *(unsigned long *)&ioaddr->cmd_addr ^= 0x03; *(unsigned long *)&ioaddr->altstatus_addr ^= 0x03; *(unsigned long *)&ioaddr->ctl_addr ^= 0x03; *(unsigned long *)&ioaddr->error_addr ^= 0x03; *(unsigned long *)&ioaddr->feature_addr ^= 0x03; *(unsigned long *)&ioaddr->nsect_addr ^= 0x03; *(unsigned long *)&ioaddr->lbal_addr ^= 0x03; *(unsigned long *)&ioaddr->lbam_addr ^= 0x03; *(unsigned long *)&ioaddr->lbah_addr ^= 0x03; *(unsigned long *)&ioaddr->device_addr ^= 0x03; *(unsigned long *)&ioaddr->status_addr ^= 0x03; *(unsigned long *)&ioaddr->command_addr ^= 0x03; raw_cmd ^= 0x03; raw_ctl ^= 0x03; #endif ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", raw_cmd, raw_ctl); }
static int __devinit sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id) { static const struct ata_port_info info = { .sht = &sil680_sht, .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = 0x1f, .mwdma_mask = 0x07, .udma_mask = ATA_UDMA6, .port_ops = &sil680_port_ops }; static const struct ata_port_info info_slow = { .sht = &sil680_sht, .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = 0x1f, .mwdma_mask = 0x07, .udma_mask = ATA_UDMA5, .port_ops = &sil680_port_ops }; const struct ata_port_info *ppi[] = { &info, NULL }; static int printed_version; struct ata_host *host; void __iomem *mmio_base; int rc, try_mmio; if (!printed_version++) dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); switch (sil680_init_chip(pdev, &try_mmio)) { case 0: ppi[0] = &info_slow; break; case 0x30: return -ENODEV; } if (!try_mmio) goto use_ioports; /* Try to acquire MMIO resources and fallback to PIO if * that fails */ rc = pcim_enable_device(pdev); if (rc) return rc; rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME); if (rc) goto use_ioports; /* Allocate host and set it up */ host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); if (!host) return -ENOMEM; host->iomap = pcim_iomap_table(pdev); /* Setup DMA masks */ rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); if (rc) return rc; rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); if (rc) return rc; pci_set_master(pdev); /* Get MMIO base and initialize port addresses */ mmio_base = host->iomap[SIL680_MMIO_BAR]; host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00; host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80; host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a; host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a; ata_std_ports(&host->ports[0]->ioaddr); host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08; host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0; host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca; host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca; ata_std_ports(&host->ports[1]->ioaddr); /* Register & activate */ return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED, &sil680_sht); use_ioports: return ata_pci_init_one(pdev, ppi); } #ifdef CONFIG_PM static int sil680_reinit_one(struct pci_dev *pdev) { int try_mmio; sil680_init_chip(pdev, &try_mmio); return ata_pci_device_resume(pdev); } #endif static const struct pci_device_id sil680[] = { { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), }, { }, }; static struct pci_driver sil680_pci_driver = { .name = DRV_NAME, .id_table = sil680, .probe = sil680_init_one, .remove = ata_pci_remove_one, #ifdef CONFIG_PM .suspend = ata_pci_device_suspend, .resume = sil680_reinit_one, #endif }; static int __init sil680_init(void) { return pci_register_driver(&sil680_pci_driver); } static void __exit sil680_exit(void) { pci_unregister_driver(&sil680_pci_driver); }
static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) { struct ata_probe_ent *probe_ent; struct ata_port_info *ppi; int rc; unsigned int board_idx = (unsigned int) ent->driver_data; int pci_dev_busy = 0; rc = pci_enable_device(pdev); if (rc) return rc; rc = pci_request_regions(pdev, DRV_NAME); if (rc) { pci_dev_busy = 1; goto err_out; } rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); if (rc) goto err_out_regions; rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); if (rc) goto err_out_regions; ppi = &uli_port_info; probe_ent = ata_pci_init_native_mode(pdev, &ppi); if (!probe_ent) { rc = -ENOMEM; goto err_out_regions; } switch (board_idx) { case uli_5287: probe_ent->port[0].scr_addr = ULI5287_BASE; probe_ent->port[1].scr_addr = ULI5287_BASE + ULI5287_OFFS; probe_ent->n_ports = 4; probe_ent->port[2].cmd_addr = pci_resource_start(pdev, 0) + 8; probe_ent->port[2].altstatus_addr = probe_ent->port[2].ctl_addr = (pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS) + 4; probe_ent->port[2].bmdma_addr = pci_resource_start(pdev, 4) + 16; probe_ent->port[2].scr_addr = ULI5287_BASE + ULI5287_OFFS*4; probe_ent->port[3].cmd_addr = pci_resource_start(pdev, 2) + 8; probe_ent->port[3].altstatus_addr = probe_ent->port[3].ctl_addr = (pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS) + 4; probe_ent->port[3].bmdma_addr = pci_resource_start(pdev, 4) + 24; probe_ent->port[3].scr_addr = ULI5287_BASE + ULI5287_OFFS*5; ata_std_ports(&probe_ent->port[2]); ata_std_ports(&probe_ent->port[3]); break; case uli_5289: probe_ent->port[0].scr_addr = ULI5287_BASE; probe_ent->port[1].scr_addr = ULI5287_BASE + ULI5287_OFFS; break; case uli_5281: probe_ent->port[0].scr_addr = ULI5281_BASE; probe_ent->port[1].scr_addr = ULI5281_BASE + ULI5281_OFFS; break; default: BUG(); break; } pci_set_master(pdev); pci_intx(pdev, 1); /* FIXME: check ata_device_add return value */ ata_device_add(probe_ent); kfree(probe_ent); return 0; err_out_regions: pci_release_regions(pdev); err_out: if (!pci_dev_busy) pci_disable_device(pdev); return rc; }
static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id) { u8 pcicfg; void __iomem *iomap[5]; static struct ata_probe_ent probe[2]; int ports = 0; /* IDE port enable bits */ pci_read_config_byte(dev, 0x60, &pcicfg); /* Check if the ATA ports are enabled */ if ((pcicfg & 3) == 0) return -ENODEV; if ((pcicfg & 0x40) == 0) { printk(KERN_WARNING DRV_NAME ": DMA mode disabled. Enabling.\n"); pci_write_config_byte(dev, 0x60, pcicfg | 0x40); } /* Perform set up for DMA */ if (pci_enable_device_bars(dev, 1<<2)) { printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n"); return -ENODEV; } pci_set_master(dev); if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n"); return -ENODEV; } if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) { printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n"); return -ENODEV; } /* Map IO ports */ iomap[0] = devm_ioport_map(&dev->dev, 0x1F0, 8); iomap[1] = devm_ioport_map(&dev->dev, 0x3F6, 1); iomap[2] = devm_ioport_map(&dev->dev, 0x170, 8); iomap[3] = devm_ioport_map(&dev->dev, 0x376, 1); iomap[4] = pcim_iomap(dev, 2, 0); if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4]) return -ENOMEM; /* We have to do our own plumbing as the PCI setup for this chipset is non-standard so we can't punt to the libata code */ INIT_LIST_HEAD(&probe[0].node); probe[0].dev = pci_dev_to_dev(dev); probe[0].port_ops = &cs5520_port_ops; probe[0].sht = &cs5520_sht; probe[0].pio_mask = 0x1F; probe[0].mwdma_mask = id->driver_data; probe[0].irq = 14; probe[0].irq_flags = 0; probe[0].port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST; probe[0].n_ports = 1; probe[0].port[0].cmd_addr = iomap[0]; probe[0].port[0].ctl_addr = iomap[1]; probe[0].port[0].altstatus_addr = iomap[1]; probe[0].port[0].bmdma_addr = iomap[4]; /* The secondary lurks at different addresses but is otherwise the same beastie */ probe[1] = probe[0]; INIT_LIST_HEAD(&probe[1].node); probe[1].irq = 15; probe[1].port[0].cmd_addr = iomap[2]; probe[1].port[0].ctl_addr = iomap[3]; probe[1].port[0].altstatus_addr = iomap[3]; probe[1].port[0].bmdma_addr = iomap[4] + 8; /* Let libata fill in the port details */ ata_std_ports(&probe[0].port[0]); ata_std_ports(&probe[1].port[0]); /* Now add the ports that are active */ if (pcicfg & 1) ports += ata_device_add(&probe[0]); if (pcicfg & 2) ports += ata_device_add(&probe[1]); if (ports) return 0; return -ENODEV; }
static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) { struct ata_probe_ent *probe_ent = NULL; int rc; u32 genctl; rc = pci_enable_device(pdev); if (rc) return rc; rc = pci_request_regions(pdev, DRV_NAME); if (rc) goto err_out; rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); if (rc) goto err_out_regions; rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); if (rc) goto err_out_regions; probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); if (!probe_ent) { rc = -ENOMEM; goto err_out_regions; } memset(probe_ent, 0, sizeof(*probe_ent)); probe_ent->pdev = pdev; INIT_LIST_HEAD(&probe_ent->node); probe_ent->sht = &sis_sht; probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET | ATA_FLAG_NO_LEGACY; /* check and see if the SCRs are in IO space or PCI cfg space */ pci_read_config_dword(pdev, SIS_GENCTL, &genctl); if ((genctl & GENCTL_IOMAPPED_SCR) == 0) probe_ent->host_flags |= SIS_FLAG_CFGSCR; /* if hardware thinks SCRs are in IO space, but there are * no IO resources assigned, change to PCI cfg space. */ if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) && ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) || (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) { genctl &= ~GENCTL_IOMAPPED_SCR; pci_write_config_dword(pdev, SIS_GENCTL, genctl); probe_ent->host_flags |= SIS_FLAG_CFGSCR; } probe_ent->pio_mask = 0x03; probe_ent->udma_mask = 0x7f; probe_ent->port_ops = &sis_ops; probe_ent->port[0].cmd_addr = pci_resource_start(pdev, 0); ata_std_ports(&probe_ent->port[0]); probe_ent->port[0].ctl_addr = pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS; probe_ent->port[0].bmdma_addr = pci_resource_start(pdev, 4); if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) probe_ent->port[0].scr_addr = pci_resource_start(pdev, SIS_SCR_PCI_BAR); probe_ent->port[1].cmd_addr = pci_resource_start(pdev, 2); ata_std_ports(&probe_ent->port[1]); probe_ent->port[1].ctl_addr = pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS; probe_ent->port[1].bmdma_addr = pci_resource_start(pdev, 4) + 8; if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) probe_ent->port[1].scr_addr = pci_resource_start(pdev, SIS_SCR_PCI_BAR) + 64; probe_ent->n_ports = 2; probe_ent->irq = pdev->irq; probe_ent->irq_flags = SA_SHIRQ; pci_set_master(pdev); pci_enable_intx(pdev); /* FIXME: check ata_device_add return value */ ata_device_add(probe_ent); kfree(probe_ent); return 0; err_out_regions: pci_release_regions(pdev); err_out: pci_disable_device(pdev); return rc; }
static int __devinit cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id) { static const unsigned int cmd_port[] = { 0x1F0, 0x170 }; static const unsigned int ctl_port[] = { 0x3F6, 0x376 }; struct ata_port_info pi = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = 0x1f, .port_ops = &cs5520_port_ops, }; const struct ata_port_info *ppi[2]; u8 pcicfg; void __iomem *iomap[5]; struct ata_host *host; struct ata_ioports *ioaddr; int i, rc; /* IDE port enable bits */ pci_read_config_byte(pdev, 0x60, &pcicfg); /* Check if the ATA ports are enabled */ if ((pcicfg & 3) == 0) return -ENODEV; ppi[0] = ppi[1] = &ata_dummy_port_info; if (pcicfg & 1) ppi[0] = π if (pcicfg & 2) ppi[1] = π if ((pcicfg & 0x40) == 0) { dev_printk(KERN_WARNING, &pdev->dev, "DMA mode disabled. Enabling.\n"); pci_write_config_byte(pdev, 0x60, pcicfg | 0x40); } pi.mwdma_mask = id->driver_data; host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); if (!host) return -ENOMEM; /* Perform set up for DMA */ if (pci_enable_device_io(pdev)) { printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n"); return -ENODEV; } if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n"); return -ENODEV; } if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n"); return -ENODEV; } /* Map IO ports and initialize host accordingly */ iomap[0] = devm_ioport_map(&pdev->dev, cmd_port[0], 8); iomap[1] = devm_ioport_map(&pdev->dev, ctl_port[0], 1); iomap[2] = devm_ioport_map(&pdev->dev, cmd_port[1], 8); iomap[3] = devm_ioport_map(&pdev->dev, ctl_port[1], 1); iomap[4] = pcim_iomap(pdev, 2, 0); if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4]) return -ENOMEM; ioaddr = &host->ports[0]->ioaddr; ioaddr->cmd_addr = iomap[0]; ioaddr->ctl_addr = iomap[1]; ioaddr->altstatus_addr = iomap[1]; ioaddr->bmdma_addr = iomap[4]; ata_std_ports(ioaddr); ata_port_desc(host->ports[0], "cmd 0x%x ctl 0x%x", cmd_port[0], ctl_port[0]); ata_port_pbar_desc(host->ports[0], 4, 0, "bmdma"); ioaddr = &host->ports[1]->ioaddr; ioaddr->cmd_addr = iomap[2]; ioaddr->ctl_addr = iomap[3]; ioaddr->altstatus_addr = iomap[3]; ioaddr->bmdma_addr = iomap[4] + 8; ata_std_ports(ioaddr); ata_port_desc(host->ports[1], "cmd 0x%x ctl 0x%x", cmd_port[1], ctl_port[1]); ata_port_pbar_desc(host->ports[1], 4, 8, "bmdma"); /* activate the host */ pci_set_master(pdev); rc = ata_host_start(host); if (rc) return rc; for (i = 0; i < 2; i++) { static const int irq[] = { 14, 15 }; struct ata_port *ap = host->ports[i]; if (ata_port_is_dummy(ap)) continue; rc = devm_request_irq(&pdev->dev, irq[ap->port_no], ata_interrupt, 0, DRV_NAME, host); if (rc) return rc; ata_port_desc(ap, "irq %d", irq[i]); } return ata_host_register(host, &cs5520_sht); } #ifdef CONFIG_PM /** * cs5520_reinit_one - device resume * @pdev: PCI device * * Do any reconfiguration work needed by a resume from RAM. We need * to restore DMA mode support on BIOSen which disabled it */ static int cs5520_reinit_one(struct pci_dev *pdev) { u8 pcicfg; pci_read_config_byte(pdev, 0x60, &pcicfg); if ((pcicfg & 0x40) == 0) pci_write_config_byte(pdev, 0x60, pcicfg | 0x40); return ata_pci_device_resume(pdev); }
static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) { static int printed_version; struct ata_probe_ent *probe_ent = NULL; unsigned long base; void *mmio_base; int rc; if (!printed_version++) printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); /* * If this driver happens to only be useful on Apple's K2, then * we should check that here as it has a normal Serverworks ID */ rc = pci_enable_device(pdev); if (rc) return rc; rc = pci_request_regions(pdev, DRV_NAME); if (rc) goto err_out; rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); if (rc) goto err_out_regions; probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); if (probe_ent == NULL) { rc = -ENOMEM; goto err_out_regions; } memset(probe_ent, 0, sizeof(*probe_ent)); INIT_LIST_HEAD(&probe_ent->node); probe_ent->pdev = pdev; probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops; probe_ent->sht = sil_port_info[ent->driver_data].sht; probe_ent->n_ports = 2; probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask; probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask; probe_ent->irq = pdev->irq; probe_ent->irq_flags = SA_SHIRQ; probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags; mmio_base = ioremap(pci_resource_start(pdev, 5), pci_resource_len(pdev, 5)); if (mmio_base == NULL) { rc = -ENOMEM; goto err_out_free_ent; } probe_ent->mmio_base = mmio_base; base = (unsigned long) mmio_base; probe_ent->port[0].cmd_addr = base + SIL_IDE0_TF; probe_ent->port[0].ctl_addr = base + SIL_IDE0_CTL; probe_ent->port[0].bmdma_addr = base + SIL_IDE0_BMDMA; probe_ent->port[0].scr_addr = base + SIL_IDE0_SCR; ata_std_ports(&probe_ent->port[0]); probe_ent->port[1].cmd_addr = base + SIL_IDE1_TF; probe_ent->port[1].ctl_addr = base + SIL_IDE1_CTL; probe_ent->port[1].bmdma_addr = base + SIL_IDE1_BMDMA; probe_ent->port[1].scr_addr = base + SIL_IDE1_SCR; ata_std_ports(&probe_ent->port[1]); pci_set_master(pdev); /* FIXME: check ata_device_add return value */ ata_device_add(probe_ent); kfree(probe_ent); return 0; err_out_free_ent: kfree(probe_ent); err_out_regions: pci_release_regions(pdev); err_out: pci_disable_device(pdev); return rc; }
static int __devinit cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id) { struct ata_port_info pi = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = 0x1f, .port_ops = &cs5520_port_ops, }; const struct ata_port_info *ppi[2]; u8 pcicfg; void *iomap[5]; struct ata_host *host; struct ata_ioports *ioaddr; int i, rc; /* IDE port enable bits */ pci_read_config_byte(pdev, 0x60, &pcicfg); /* Check if the ATA ports are enabled */ if ((pcicfg & 3) == 0) return -ENODEV; ppi[0] = ppi[1] = &ata_dummy_port_info; if (pcicfg & 1) ppi[0] = π if (pcicfg & 2) ppi[1] = π if ((pcicfg & 0x40) == 0) { dev_printk(KERN_WARNING, &pdev->dev, "DMA mode disabled. Enabling.\n"); pci_write_config_byte(pdev, 0x60, pcicfg | 0x40); } pi.mwdma_mask = id->driver_data; host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); if (!host) return -ENOMEM; /* Perform set up for DMA */ if (pci_enable_device_bars(pdev, 1<<2)) { printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n"); return -ENODEV; } if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n"); return -ENODEV; } if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n"); return -ENODEV; } /* Map IO ports and initialize host accordingly */ iomap[0] = devm_ioport_map(&pdev->dev, 0x1F0, 8); iomap[1] = devm_ioport_map(&pdev->dev, 0x3F6, 1); iomap[2] = devm_ioport_map(&pdev->dev, 0x170, 8); iomap[3] = devm_ioport_map(&pdev->dev, 0x376, 1); iomap[4] = pcim_iomap(pdev, 2, 0); if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4]) return -ENOMEM; ioaddr = &host->ports[0]->ioaddr; ioaddr->cmd_addr = iomap[0]; ioaddr->ctl_addr = iomap[1]; ioaddr->altstatus_addr = iomap[1]; ioaddr->bmdma_addr = iomap[4]; ata_std_ports(ioaddr); ioaddr = &host->ports[1]->ioaddr; ioaddr->cmd_addr = iomap[2]; ioaddr->ctl_addr = iomap[3]; ioaddr->altstatus_addr = iomap[3]; ioaddr->bmdma_addr = iomap[4] + 8; ata_std_ports(ioaddr); /* activate the host */ pci_set_master(pdev); rc = ata_host_start(host); if (rc) return rc; for (i = 0; i < 2; i++) { static const int irq[] = { 14, 15 }; struct ata_port *ap = host->ports[i]; if (ata_port_is_dummy(ap)) continue; rc = devm_request_irq(&pdev->dev, irq[ap->port_no], ata_interrupt, 0, DRV_NAME, host); if (rc) return rc; if (i == 0) host->irq = irq[0]; else host->irq2 = irq[1]; } return ata_host_register(host, &cs5520_sht); } /** * cs5520_remove_one - device unload * @pdev: PCI device being removed * * Handle an unplug/unload event for a PCI device. Unload the * PCI driver but do not use the default handler as we manage * resources ourself and *MUST NOT* disable the device as it has * other functions. */ static void __devexit cs5520_remove_one(struct pci_dev *pdev) { struct device *dev = pci_dev_to_dev(pdev); struct ata_host *host = dev_get_drvdata(dev); ata_host_detach(host); } #ifdef CONFIG_PM /** * cs5520_reinit_one - device resume * @pdev: PCI device * * Do any reconfiguration work needed by a resume from RAM. We need * to restore DMA mode support on BIOSen which disabled it */ static int cs5520_reinit_one(struct pci_dev *pdev) { u8 pcicfg; pci_read_config_byte(pdev, 0x60, &pcicfg); if ((pcicfg & 0x40) == 0) pci_write_config_byte(pdev, 0x60, pcicfg | 0x40); return ata_pci_device_resume(pdev); }