void ath79_device_reset_clear(u32 mask)
{
unsigned long flags;
u32 reg;
u32 t;
if (soc_is_ar71xx())
reg = AR71XX_RESET_REG_RESET_MODULE;
else if (soc_is_ar724x())
reg = AR724X_RESET_REG_RESET_MODULE;
else if (soc_is_ar913x())
reg = AR913X_RESET_REG_RESET_MODULE;
else if (soc_is_ar933x())
reg = AR933X_RESET_REG_RESET_MODULE;
else if (soc_is_ar934x())
reg = AR934X_RESET_REG_RESET_MODULE;
else if (soc_is_qca953x())
reg = QCA953X_RESET_REG_RESET_MODULE;
else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE;
else
panic("Reset register not defined for this SOC");
spin_lock_irqsave(&ath79_device_reset_lock, flags);
t = ath79_reset_rr(reg);
ath79_reset_wr(reg, t & ~mask);
spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
}
static inline void ath79_wdt_enable(void)
{
ath79_wdt_keepalive();
ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
/* flush write */
ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
}
static void __init ds_setup(void)
{
#ifdef DS2_PREV_RESET_PIN
u32 t;
#endif
ds_common_setup();
ath79_register_leds_gpio(-1, ARRAY_SIZE(ds_leds_gpio),
ds_leds_gpio);
ath79_register_gpio_keys_polled(-1, DS_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ds_gpio_keys),
ds_gpio_keys);
ath79_register_usb();
//Disable the Function for some pins to have GPIO functionality active
// GPIO6-7-8 and GPIO11
ath79_gpio_function_setup(AR933X_GPIO_FUNC_JTAG_DISABLE | AR933X_GPIO_FUNC_I2S_MCK_EN, 0);
ath79_gpio_function2_setup(AR933X_GPIO_FUNC2_JUMPSTART_DISABLE, 0);
printk("Setting DogStick2 GPIO\n");
#ifdef DS2_PREV_RESET_PIN
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
// Put the avr reset to high
if (gpio_request_one(DS_GPIO_AVR_RESET_DS2,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"OE-1") != 0)
printk("Error setting GPIO OE\n");
gpio_unexport(DS_GPIO_AVR_RESET_DS2);
gpio_free(DS_GPIO_AVR_RESET_DS2);
#endif
// enable OE of level shifter
if (gpio_request_one(DS_GPIO_OE,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"OE-1") != 0)
printk("Error setting GPIO OE\n");
#ifdef DS1
if (gpio_request_one(DS_GPIO_OE2,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"OE-2") != 0)
printk("Error setting GPIO OE2\n");
#else
if (gpio_request_one(DS_GPIO_UART_ENA,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"UART-ENA") != 0)
printk("Error setting GPIO Uart Enable\n");
// enable OE of level shifter
if (gpio_request_one(DS_GPIO_OE2,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"OE-2") != 0)
printk("Error setting GPIO OE2\n");
#endif
}
static void __noreturn ath79_restart_soc(struct restart_handler *rst)
{
ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, AR71XX_RESET_FULL_CHIP);
/*
* Used to command a full chip reset. This is the software equivalent of
* pulling the reset pin. The system will reboot with PLL disabled.
* Always zero when read.
*/
hang();
/*NOTREACHED*/
}
static inline void ath79_wdt_enable(void)
{
ath79_wdt_keepalive();
/*
* Updating the TIMER register requires a few microseconds
* on the AR934x SoCs at least. Use a small delay to ensure
* that the TIMER register is updated within the hardware
* before enabling the watchdog.
*/
udelay(2);
ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
}
static void __init hornet_ub_gpio_setup(void)
{
u32 t;
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
ath79_set_usb_power_gpio(HORNET_UB_GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH,
"USB power");
}
static void __init om2p_lc_setup(void)
{
u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000);
u32 t;
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
ath79_register_m25p80(&om2p_lc_flash_data);
om2p_leds_gpio[0].gpio = OM2P_LC_GPIO_LED_POWER;
om2p_leds_gpio[1].gpio = OM2P_LC_GPIO_LED_RED;
om2p_leds_gpio[2].gpio = OM2P_LC_GPIO_LED_YELLOW;
om2p_leds_gpio[3].gpio = OM2P_LC_GPIO_LED_GREEN;
om2p_leds_gpio[4].gpio = OM2P_LC_GPIO_LED_LAN;
om2p_leds_gpio[5].gpio = OM2P_LC_GPIO_LED_WAN;
ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
om2p_leds_gpio);
om2p_gpio_keys[0].gpio = OM2P_LC_GPIO_BTN_RESET;
ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om2p_gpio_keys),
om2p_gpio_keys);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_wmac(art, NULL);
}
static void __init cus227_audio_setup(void)
{
u32 t;
/* Reset I2S internal controller */
t = ath79_reset_rr(AR71XX_RESET_REG_RESET_MODULE);
ath79_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t | AR934X_RESET_I2S );
udelay(1);
/* GPIO configuration
Please note that the value in direction_output doesn't really matter
here as GPIOs are configured to relay internal data signal
*/
gpio_request(CUS227_GPIO_I2S_CLK, "I2S CLK");
ath79_gpio_output_select(CUS227_GPIO_I2S_CLK, AR934X_GPIO_OUT_MUX_I2S_CLK);
gpio_direction_output(CUS227_GPIO_I2S_CLK, 0);
gpio_request(CUS227_GPIO_I2S_WS, "I2S WS");
ath79_gpio_output_select(CUS227_GPIO_I2S_WS, AR934X_GPIO_OUT_MUX_I2S_WS);
gpio_direction_output(CUS227_GPIO_I2S_WS, 0);
gpio_request(CUS227_GPIO_I2S_SD, "I2S SD");
ath79_gpio_output_select(CUS227_GPIO_I2S_SD, AR934X_GPIO_OUT_MUX_I2S_SD);
gpio_direction_output(CUS227_GPIO_I2S_SD, 0);
gpio_request(CUS227_GPIO_I2S_MCLK, "I2S MCLK");
ath79_gpio_output_select(CUS227_GPIO_I2S_MCLK, AR934X_GPIO_OUT_MUX_I2S_MCK);
gpio_direction_output(CUS227_GPIO_I2S_MCLK, 0);
gpio_request(CUS227_GPIO_SPDIF_OUT, "SPDIF OUT");
ath79_gpio_output_select(CUS227_GPIO_SPDIF_OUT, AR934X_GPIO_OUT_MUX_SPDIF_OUT);
gpio_direction_output(CUS227_GPIO_SPDIF_OUT, 0);
gpio_request(CUS227_GPIO_I2S_MIC_SD, "I2S MIC_SD");
ath79_gpio_input_select(CUS227_GPIO_I2S_MIC_SD, AR934X_GPIO_IN_MUX_I2S_MIC_SD);
gpio_direction_input(CUS227_GPIO_I2S_MIC_SD);
/* Init stereo block registers in default configuration */
ath79_audio_setup();
}
static void __init ds_setup(void)
{
u32 t=0;
ds_common_setup();
ath79_register_leds_gpio(-1, ARRAY_SIZE(ds_leds_gpio), ds_leds_gpio);
ath79_register_gpio_keys_polled(-1, DS_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ds_gpio_keys), ds_gpio_keys);
ath79_register_usb();
// use the swtich_led directly form sysfs
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN);
/*
* Disable the Function for some pins to have GPIO functionality active
* GPIO6-7-8 and GPIO11
*/
ath79_gpio_function_setup(GPIO_FUNC_SET, GPIO_FUNC_CLEAR);
ath79_gpio_function2_setup(GPIO_FUNC2_SET, GPIO_FUNC2_CLEAR);
pr_info("mach-linino: setting GPIO\n");
/* Enable GPIO26 instead of MDC function */
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
/* enable OE of level shifters */
ds_setup_level_shifter_oe();
/* enable uart */
ds_setup_uart_enable();
/* Register Software SPI controller */
ds_register_spi();
}
static void __init ubnt_airgateway_setup(void)
{
u32 t;
u8 *mac0 = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airgateway_gpio_leds),
ubnt_airgateway_gpio_leds);
ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
ARRAY_SIZE(airgateway_gpio_keys),
airgateway_gpio_keys);
ath79_init_mac(ath79_eth1_data.mac_addr, mac0, 0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(1);
ath79_register_eth(0);
ath79_register_wmac(ee, NULL);
}
static inline void ath79_wdt_disable(void)
{
ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE);
/* flush write */
ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
}
static inline void ath79_wdt_keepalive(void)
{
ath79_reset_wr(AR71XX_RESET_REG_WDOG, wdt_freq * timeout);
/* flush write */
ath79_reset_rr(AR71XX_RESET_REG_WDOG);
}
