static void __init domino_setup(void)
{
/* ART base address */
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
/* register flash. */
ath79_register_m25p80(NULL);
/* register gpio LEDs and keys */
ath79_register_leds_gpio(-1, ARRAY_SIZE(domino_leds_gpio),
domino_leds_gpio);
ath79_register_gpio_keys_polled(-1, DOMINO_KEYS_POLL_INTERVAL,
ARRAY_SIZE(domino_gpio_keys),
domino_gpio_keys);
gpio_request_one(DOMINO_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
/* enable usb */
ath79_register_usb();
/* register eth0 as WAN, eth1 as LAN */
ath79_init_mac(ath79_eth0_data.mac_addr, art+DOMINO_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art+DOMINO_MAC1_OFFSET, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);
/* register wireless mac with cal data */
ath79_register_wmac(art + DOMINO_CALDATA_OFFSET, art + DOMINO_WMAC_MAC_OFFSET);
}
static void __init e600g_v2_common_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f050400);
u8 *art = (u8 *) KSEG1ADDR(0x1f061000);
ath79_register_m25p80(NULL);
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_mdio(0, 0x0);
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = 0xfe;
/* LAN */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.speed = SPEED_100;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_register_eth(0);
/* WAN */
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.phy_mask = BIT(0);
ath79_eth1_data.speed = SPEED_1000;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_eth(1);
ath79_register_pci();
ath79_register_usb();
ath79_register_wmac(art, NULL);
}
static void __init tl_mr11u_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_setup_ar933x_phy4_switch(false, true);
ath79_register_m25p80(&tl_mr11u_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr11u_leds_gpio),
tl_mr11u_leds_gpio);
ath79_register_gpio_keys_polled(-1, TL_MR11U_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_mr11u_gpio_keys),
tl_mr11u_gpio_keys);
gpio_request(TL_MR11U_GPIO_USB_POWER, "USB power");
gpio_direction_output(TL_MR11U_GPIO_USB_POWER, 1);
ath79_register_usb();
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_eth0_data.phy_mask = BIT(0);
ath79_register_wmac(ee, mac);
}
static void __init common_setup(unsigned usb_power_gpio, bool sec_ethernet)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_m25p80(&tl_wr703n_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr703n_leds_gpio),
tl_wr703n_leds_gpio);
ath79_register_gpio_keys_polled(-1, TL_WR703N_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wr703n_gpio_keys),
tl_wr703n_gpio_keys);
gpio_request_one(usb_power_gpio,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_register_eth(0);
if (sec_ethernet)
{
ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
ath79_register_eth(1);
}
tplink_register_builtin_wmac1(0x1000, mac, 0);
}
static void __init ap121f_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1f040000);
ath79_register_m25p80(NULL);
ath79_setup_ar933x_phy4_switch(false, false);
/* LAN */
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0);
ath79_register_eth(0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121f_leds_gpio),
ap121f_leds_gpio);
ath79_register_gpio_keys_polled(-1, AP121F_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap121f_gpio_keys),
ap121f_gpio_keys);
gpio_request_one(AP121F_GPIO_MICROSD_EN,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"microSD enable");
ath79_register_wmac(art + AP121F_WMAC_CALDATA_OFFSET, NULL);
ath79_register_usb();
}
static void __init som9331_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_setup_ar933x_phy4_switch(true, true);
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
ath79_register_m25p80(&som9331_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(som9331_leds_gpio),
som9331_leds_gpio);
ath79_register_gpio_keys_polled(-1, SOM9331_KEYS_POLL_INTERVAL,
ARRAY_SIZE(som9331_gpio_keys),
som9331_gpio_keys);
ath79_register_usb();
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
ath79_register_mdio(0, 0x0);
/* LAN ports */
ath79_register_eth(1);
/* WAN port */
ath79_register_eth(0);
ath79_register_wmac(ee, mac);
}
static void __init bsb_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false,false);
ath79_register_leds_gpio(-1, ARRAY_SIZE(bsb_leds_gpio),
bsb_leds_gpio);
ath79_register_gpio_keys_polled(-1, BSB_KEYS_POLL_INTERVAL,
ARRAY_SIZE(bsb_gpio_keys),
bsb_gpio_keys);
ath79_register_usb();
ath79_register_m25p80(NULL);
ath79_init_mac(ath79_eth0_data.mac_addr, art + BSB_MAC_OFFSET, 1);
ath79_init_mac(ath79_eth1_data.mac_addr, art + BSB_MAC_OFFSET, 2);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_wmac(art + BSB_CALDATA_OFFSET,
art + BSB_MAC_OFFSET);
}
static void __init lima_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1f080000);
ath79_register_m25p80(NULL);
ath79_register_gpio_keys_polled(-1, LIMA_KEYS_POLL_INTERVAL,
ARRAY_SIZE(lima_gpio_keys),
lima_gpio_keys);
ath79_setup_ar933x_phy4_switch(true, true);
ath79_init_mac(ath79_eth0_data.mac_addr, art + LIMA_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + LIMA_MAC1_OFFSET, 0);
ath79_register_mdio(0, ~LIMA_ETH_PHYS);
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask |= BIT(0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_data.phy_mask = BIT(1);
ath79_register_eth(1);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.phy_mask = BIT(0);
ath79_register_eth(0);
ath79_register_wmac(art + LIMA_CALDATA_OFFSET, NULL);
ath79_register_usb();
ath79_register_pci();
}
static void __init tl_ap151_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f00fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&tl_wdr6500_v2_flash_data);
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_mdio(0, 0x0);
/* WAN */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_register_eth(0);
/* LAN */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_data.speed = SPEED_1000;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_eth(1);
ath79_init_mac(tmpmac, mac, -1);
ath79_register_wmac(ee + TL_WDR6500_V2_WMAC_CALDATA_OFFSET, tmpmac);
ath79_register_pci();
ath79_register_usb();
}
static void __init tl_mr3020_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_setup_ar933x_phy4_switch(false, true);
ath79_register_m25p80(&tl_mr3020_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3020_leds_gpio),
tl_mr3020_leds_gpio);
ath79_register_gpio_keys_polled(-1, TL_MR3020_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_mr3020_gpio_keys),
tl_mr3020_gpio_keys);
ath79_set_usb_power_gpio(TL_MR3020_GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH,
"USB power");
ath79_register_usb();
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_eth0_data.phy_mask = BIT(0);
ath79_register_wmac(ee, mac);
}
static void __init antminer_s1_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ANTMINER_S1_leds_gpio),
ANTMINER_S1_leds_gpio);
ath79_register_gpio_keys_polled(-1, ANTMINER_S1_KEYSPOLL_INTERVAL,
ARRAY_SIZE(ANTMINER_S1_GPIO_keys),
ANTMINER_S1_GPIO_keys);
gpio_request_one(ANTMINER_S1_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
ath79_register_m25p80(&ANTMINER_S1_flash_data);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
}
static void __init cf_exxxn_qca953x_eth_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f010000);
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_mdio(0, 0x0);
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask |= BIT(4);
/* LAN */
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 2);
ath79_register_eth(1);
/* WAN */
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.phy_mask = BIT(4);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_eth(0);
}
static void __init carambola2_common_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
/* Disable UART, enabling GPIO 9 and GPIO 10 */
ath79_gpio_function_disable(AR933X_GPIO_FUNC_UART_EN);
/* Enabling internal CS1, disable GPIO 9 */
ath79_gpio_function_enable(AR933X_GPIO_FUNC_SPI_CS_EN1);
ath79_register_m25p80i_multi(NULL);
ath79_register_wmac(art + CARAMBOLA2_CALDATA_OFFSET,
art + CARAMBOLA2_WMAC_MAC_OFFSET);
ath79_setup_ar933x_phy4_switch(true, true);
ath79_init_mac(ath79_eth0_data.mac_addr, art + CARAMBOLA2_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + CARAMBOLA2_MAC1_OFFSET, 0);
ath79_register_mdio(0, 0x0);
/* LAN ports */
ath79_register_eth(1);
/* WAN port */
ath79_register_eth(0);
// spi_register_board_info(ath79_spi_info, ARRAY_SIZE(ath79_spi_info));
}
static void __init gl_inet_setup(void)
{
/* get the mac address which is stored in the 1st 64k uboot MTD */
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
/* get the art address, which is the last 64K. By using
0x1fff1000, it doesn't matter it is 4M, 8M or 16M flash */
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
/* register flash. MTD will use tp-link parser to parser MTD */
ath79_register_m25p80(&gl_inet_flash_data);
/* register gpio LEDs and keys */
ath79_register_leds_gpio(-1, ARRAY_SIZE(gl_inet_leds_gpio),
gl_inet_leds_gpio);
ath79_register_gpio_keys_polled(-1, GL_INET_KEYS_POLL_INTERVAL,
ARRAY_SIZE(gl_inet_gpio_keys),
gl_inet_gpio_keys);
/* enable usb */
ath79_register_usb();
/* register eth0 as WAN, eth1 as LAN */
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_eth(1);
/* register wireless mac with cal data */
ath79_register_wmac(ee, mac);
}
static void __init tl_ap143_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&tl_wr841n_v9_flash_data);
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_mdio(0, 0x0);
/* LAN */
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_eth(1);
/* WAN */
ath79_switch_data.phy4_mii_en = 1;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_register_eth(0);
ath79_init_mac(tmpmac, mac, 0);
ath79_register_wmac(ee, tmpmac);
}
static void __init common_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = ath79_get_eeprom();
/* Disable hardware control LAN1 and LAN2 LEDs, enabling GPIO14 and GPIO15 */
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_m25p80(&tl_mr11u_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr11u_leds_gpio),
tl_mr11u_leds_gpio);
ath79_register_usb();
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_wmac(ee, mac);
}
static void __init gl_mifi_setup(void)
{
/* ART base address */
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
/* register flash. */
ath79_register_m25p80(NULL);
/* register gpio LEDs and keys */
ath79_register_leds_gpio(-1, ARRAY_SIZE(gl_mifi_leds_gpio),
gl_mifi_leds_gpio);
ath79_register_gpio_keys_polled(-1, GL_MIFI_KEYS_POLL_INTERVAL,
ARRAY_SIZE(gl_mifi_gpio_keys),
gl_mifi_gpio_keys);
/* enable usb */
ath79_register_usb();
/* register eth0 as WAN, eth1 as LAN */
ath79_init_mac(ath79_eth0_data.mac_addr, art+GL_MIFI_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art+GL_MIFI_MAC1_OFFSET, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);
/* register wireless mac with cal data */
ath79_register_wmac(art + GL_MIFI_CALDATA_OFFSET, art + GL_MIFI_WMAC_MAC_OFFSET);
}
static void __init dir_505_a1_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(DIR_505A1_ART_ADDRESS);
u8 lan_mac[ETH_ALEN];
u8 wan_mac[ETH_ALEN];
ath79_setup_ar933x_phy4_switch(false, false);
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
gpio_request_one(DIR_505A1_GPIO_WAN_LED_ENABLE,
GPIOF_OUT_INIT_LOW, "WAN LED enable");
ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_505_a1_leds_gpio),
dir_505_a1_leds_gpio);
ath79_register_gpio_keys_polled(1, DIR_505A1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dir_505_a1_gpio_keys),
dir_505_a1_gpio_keys);
ath79_register_m25p80(NULL);
ath79_register_usb();
dir_505_a1_read_ascii_mac(lan_mac, DIR_505A1_LAN_MAC_ADDRESS);
dir_505_a1_read_ascii_mac(wan_mac, DIR_505A1_WAN_MAC_ADDRESS);
ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(1);
ath79_register_eth(0);
ath79_register_wmac(art + DIR_505A1_CALDATA_OFFSET, lan_mac);
}
static void __init tew_712br_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(TEW_712BR_ART_ADDRESS);
u8 *mac = (u8 *) KSEG1ADDR(TEW_712BR_MAC_PART_ADDRESS);
u8 lan_mac[ETH_ALEN];
u8 wan_mac[ETH_ALEN];
ath79_setup_ar933x_phy4_switch(false, false);
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
gpio_request_one(TEW_712BR_GPIO_WAN_LED_ENABLE,
GPIOF_OUT_INIT_LOW, "WAN LED enable");
ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_712br_leds_gpio),
tew_712br_leds_gpio);
ath79_register_gpio_keys_polled(1, TEW_712BR_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tew_712br_gpio_keys),
tew_712br_gpio_keys);
ath79_register_m25p80(NULL);
ath79_parse_ascii_mac(mac + TEW_712BR_LAN_MAC_OFFSET, lan_mac);
ath79_parse_ascii_mac(mac + TEW_712BR_WAN_MAC_OFFSET, wan_mac);
ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(1);
ath79_register_eth(0);
ath79_register_wmac(art + TEW_712BR_CALDATA_OFFSET, wan_mac);
}
static void __init ew_dorin_router_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
static u8 mac[6];
ath79_register_m25p80(NULL);
ath79_register_usb();
if (ar93xx_wmac_read_mac_address(mac)) {
ath79_register_wmac(NULL, NULL);
} else {
ath79_register_wmac(art + DORIN_CALDATA_OFFSET,
art + DORIN_WMAC_MAC_OFFSET);
memcpy(mac, art + DORIN_WMAC_MAC_OFFSET, sizeof(mac));
}
mac[3] |= 0x40;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
mac[3] &= 0x3F;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_setup_ar933x_phy4_switch(true, true);
ath79_register_mdio(0, 0x0);
/* LAN ports */
ath79_register_eth(1);
/* WAN port */
ath79_register_eth(0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dorin_leds_gpio),
dorin_leds_gpio);
ath79_register_gpio_keys_polled(-1, DORIN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dorin_gpio_keys),
dorin_gpio_keys);
}
static void __init tl_ap143_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f3c0008);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(NULL);
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_mdio(0, 0x0);
ath79_switch_data.phy4_mii_en = 1;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.speed = SPEED_100;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -2);
ath79_register_eth(0);
ath79_init_mac(tmpmac, mac, 0);
ath79_register_wmac(ee, mac);
}
