void __init prom_init(void) { u32 reg, mask; bcm63xx_cpu_init(); /* stop any running watchdog */ bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG); bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); /* disable all hardware blocks clock for now */ if (BCMCPU_IS_6338()) mask = CKCTL_6338_ALL_SAFE_EN; else if (BCMCPU_IS_6345()) mask = CKCTL_6345_ALL_SAFE_EN; else if (BCMCPU_IS_6348()) mask = CKCTL_6348_ALL_SAFE_EN; else if (BCMCPU_IS_6358()) mask = CKCTL_6358_ALL_SAFE_EN; else if (BCMCPU_IS_6368()) mask = CKCTL_6368_ALL_SAFE_EN; else mask = 0; reg = bcm_perf_readl(PERF_CKCTL_REG); reg &= ~mask; bcm_perf_writel(reg, PERF_CKCTL_REG); /* register gpiochip */ bcm63xx_gpio_init(); /* do low level board init */ board_prom_init(); }
static void bcm63xx_external_irq_clear(unsigned int irq) { u32 reg; irq -= IRQ_EXT_BASE; reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); reg |= EXTIRQ_CFG_CLEAR(irq); bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); }
/* * external IRQs operations: mask/unmask and clear on PERF external * irq control register. */ static void bcm63xx_external_irq_mask(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXT_BASE; u32 reg; reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); reg &= ~EXTIRQ_CFG_MASK(irq); bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); }
static int bcm63xx_external_irq_set_type(unsigned int irq, unsigned int flow_type) { u32 reg; struct irq_desc *desc = irq_desc + irq; irq -= IRQ_EXT_BASE; flow_type &= IRQ_TYPE_SENSE_MASK; if (flow_type == IRQ_TYPE_NONE) flow_type = IRQ_TYPE_LEVEL_LOW; reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); switch (flow_type) { case IRQ_TYPE_EDGE_BOTH: reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); reg |= EXTIRQ_CFG_BOTHEDGE(irq); break; case IRQ_TYPE_EDGE_RISING: reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); reg |= EXTIRQ_CFG_SENSE(irq); reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); break; case IRQ_TYPE_EDGE_FALLING: reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); reg &= ~EXTIRQ_CFG_SENSE(irq); reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); break; case IRQ_TYPE_LEVEL_HIGH: reg |= EXTIRQ_CFG_LEVELSENSE(irq); reg |= EXTIRQ_CFG_SENSE(irq); break; case IRQ_TYPE_LEVEL_LOW: reg |= EXTIRQ_CFG_LEVELSENSE(irq); reg &= ~EXTIRQ_CFG_SENSE(irq); break; default: printk(KERN_ERR "bogus flow type combination given !\n"); return -EINVAL; } bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) { desc->status |= IRQ_LEVEL; desc->handle_irq = handle_level_irq; } else { desc->handle_irq = handle_edge_irq; } return 0; }
static void bcm63xx_internal_irq_unmask(struct irq_data *d) { unsigned int irq = d->irq - IRQ_INTERNAL_BASE; u32 mask; mask = bcm_perf_readl(PERF_IRQMASK_REG); mask |= (1 << irq); bcm_perf_writel(mask, PERF_IRQMASK_REG); }
static void bcm63xx_external_irq_clear(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXT_BASE; u32 reg; reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); reg |= EXTIRQ_CFG_CLEAR(irq); bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); }
/* * external IRQs operations: mask/unmask and clear on PERF external * irq control register. */ static void bcm63xx_external_irq_mask(unsigned int irq) { u32 reg; irq -= IRQ_EXT_BASE; reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); reg &= ~EXTIRQ_CFG_MASK(irq); bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); }
static void bcm63xx_internal_irq_unmask(unsigned int irq) { u32 mask; irq -= IRQ_INTERNAL_BASE; mask = bcm_perf_readl(PERF_IRQMASK_REG); mask |= (1 << irq); bcm_perf_writel(mask, PERF_IRQMASK_REG); }
static void bcm_hwclock_set(u32 mask, int enable) { u32 reg; reg = bcm_perf_readl(PERF_CKCTL_REG); if (enable) reg |= mask; else reg &= ~mask; bcm_perf_writel(reg, PERF_CKCTL_REG); }
static void enetsw_set(struct clk *clk, int enable) { if (!BCMCPU_IS_6368()) return; bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN | CKCTL_6368_SWPKT_USB_EN | CKCTL_6368_SWPKT_SAR_EN, enable); if (enable) { u32 val; val = bcm_perf_readl(PERF_SOFTRESET_6368_REG); val &= ~SOFTRESET_6368_ENETSW_MASK; bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); msleep(10); val |= SOFTRESET_6368_ENETSW_MASK; bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); msleep(10); } }
static int bcm63xx_external_irq_set_type(struct irq_data *d, unsigned int flow_type) { unsigned int irq = d->irq - IRQ_EXT_BASE; u32 reg; flow_type &= IRQ_TYPE_SENSE_MASK; if (flow_type == IRQ_TYPE_NONE) flow_type = IRQ_TYPE_LEVEL_LOW; reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); switch (flow_type) { case IRQ_TYPE_EDGE_BOTH: reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); reg |= EXTIRQ_CFG_BOTHEDGE(irq); break; case IRQ_TYPE_EDGE_RISING: reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); reg |= EXTIRQ_CFG_SENSE(irq); reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); break; case IRQ_TYPE_EDGE_FALLING: reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); reg &= ~EXTIRQ_CFG_SENSE(irq); reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); break; case IRQ_TYPE_LEVEL_HIGH: reg |= EXTIRQ_CFG_LEVELSENSE(irq); reg |= EXTIRQ_CFG_SENSE(irq); break; case IRQ_TYPE_LEVEL_LOW: reg |= EXTIRQ_CFG_LEVELSENSE(irq); reg &= ~EXTIRQ_CFG_SENSE(irq); break; default: printk(KERN_ERR "bogus flow type combination given !\n"); return -EINVAL; } bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); irqd_set_trigger_type(d, flow_type); if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) __irq_set_handler_locked(d->irq, handle_level_irq); else __irq_set_handler_locked(d->irq, handle_edge_irq); return IRQ_SET_MASK_OK_NOCOPY; }
static void xtm_set(struct clk *clk, int enable) { if (!BCMCPU_IS_6368()) return; bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN | CKCTL_6368_SWPKT_SAR_EN, enable); if (enable) { u32 val; val = bcm_perf_readl(PERF_SOFTRESET_6368_REG); val &= ~SOFTRESET_6368_SAR_MASK; bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); mdelay(1); val |= SOFTRESET_6368_SAR_MASK; bcm_perf_writel(val, PERF_SOFTRESET_6368_REG); mdelay(1); } }
static void bcm63xx_external_irq_clear(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; regaddr = get_ext_irq_perf_reg(irq); reg = bcm_perf_readl(regaddr); if (BCMCPU_IS_6348()) reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4); else reg |= EXTIRQ_CFG_CLEAR(irq % 4); bcm_perf_writel(reg, regaddr); }
/* * external IRQs operations: mask/unmask and clear on PERF external * irq control register. */ static void bcm63xx_external_irq_mask(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; regaddr = get_ext_irq_perf_reg(irq); reg = bcm_perf_readl(regaddr); if (BCMCPU_IS_6348()) reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4); else reg &= ~EXTIRQ_CFG_MASK(irq % 4); bcm_perf_writel(reg, regaddr); if (is_ext_irq_cascaded) internal_irq_mask(irq + ext_irq_start); }
static void bcm63xx_external_irq_clear(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; unsigned long flags; regaddr = get_ext_irq_perf_reg(irq); spin_lock_irqsave(&epic_lock, flags); reg = bcm_perf_readl(regaddr); if (BCMCPU_IS_6348()) reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4); else reg |= EXTIRQ_CFG_CLEAR(irq % 4); bcm_perf_writel(reg, regaddr); spin_unlock_irqrestore(&epic_lock, flags); }
/* * external IRQs operations: mask/unmask and clear on PERF external * irq control register. */ static void bcm63xx_external_irq_mask(struct irq_data *d) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; unsigned long flags; regaddr = get_ext_irq_perf_reg(irq); spin_lock_irqsave(&epic_lock, flags); reg = bcm_perf_readl(regaddr); if (BCMCPU_IS_6348()) reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4); else reg &= ~EXTIRQ_CFG_MASK(irq % 4); bcm_perf_writel(reg, regaddr); spin_unlock_irqrestore(&epic_lock, flags); if (is_ext_irq_cascaded) internal_irq_mask(irq_get_irq_data(irq + ext_irq_start)); }
void __init prom_init(void) { u32 reg, mask; bcm63xx_cpu_init(); /* stop any running watchdog */ bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG); bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); /* disable all hardware blocks clock for now */ if (BCMCPU_IS_3368()) mask = CKCTL_3368_ALL_SAFE_EN; else if (BCMCPU_IS_6328()) mask = CKCTL_6328_ALL_SAFE_EN; else if (BCMCPU_IS_6338()) mask = CKCTL_6338_ALL_SAFE_EN; else if (BCMCPU_IS_6345()) mask = CKCTL_6345_ALL_SAFE_EN; else if (BCMCPU_IS_6348()) mask = CKCTL_6348_ALL_SAFE_EN; else if (BCMCPU_IS_6358()) mask = CKCTL_6358_ALL_SAFE_EN; else if (BCMCPU_IS_6362()) mask = CKCTL_6362_ALL_SAFE_EN; else if (BCMCPU_IS_6368()) mask = CKCTL_6368_ALL_SAFE_EN; else mask = 0; reg = bcm_perf_readl(PERF_CKCTL_REG); reg &= ~mask; bcm_perf_writel(reg, PERF_CKCTL_REG); /* register gpiochip */ bcm63xx_gpio_init(); /* do low level board init */ board_prom_init(); /* set up SMP */ if (!register_bmips_smp_ops()) { /* * BCM6328 might not have its second CPU enabled, while BCM3368 * and BCM6358 need special handling for their shared TLB, so * disable SMP for now. */ if (BCMCPU_IS_6328()) { reg = bcm_readl(BCM_6328_OTP_BASE + OTP_USER_BITS_6328_REG(3)); if (reg & OTP_6328_REG3_TP1_DISABLED) bmips_smp_enabled = 0; } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) { bmips_smp_enabled = 0; } if (!bmips_smp_enabled) return; /* * The bootloader has set up the CPU1 reset vector at * 0xa000_0200. * This conflicts with the special interrupt vector (IV). * The bootloader has also set up CPU1 to respond to the wrong * IPI interrupt. * Here we will start up CPU1 in the background and ask it to * reconfigure itself then go back to sleep. */ memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20); __sync(); set_c0_cause(C_SW0); cpumask_set_cpu(1, &bmips_booted_mask); /* * FIXME: we really should have some sort of hazard barrier here */ } }
static int bcm63xx_external_irq_set_type(struct irq_data *d, unsigned int flow_type) { unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; u32 reg, regaddr; int levelsense, sense, bothedge; flow_type &= IRQ_TYPE_SENSE_MASK; if (flow_type == IRQ_TYPE_NONE) flow_type = IRQ_TYPE_LEVEL_LOW; levelsense = sense = bothedge = 0; switch (flow_type) { case IRQ_TYPE_EDGE_BOTH: bothedge = 1; break; case IRQ_TYPE_EDGE_RISING: sense = 1; break; case IRQ_TYPE_EDGE_FALLING: break; case IRQ_TYPE_LEVEL_HIGH: levelsense = 1; sense = 1; break; case IRQ_TYPE_LEVEL_LOW: levelsense = 1; break; default: printk(KERN_ERR "bogus flow type combination given !\n"); return -EINVAL; } regaddr = get_ext_irq_perf_reg(irq); reg = bcm_perf_readl(regaddr); irq %= 4; switch (bcm63xx_get_cpu_id()) { case BCM6348_CPU_ID: if (levelsense) reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq); else reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq); if (sense) reg |= EXTIRQ_CFG_SENSE_6348(irq); else reg &= ~EXTIRQ_CFG_SENSE_6348(irq); if (bothedge) reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq); else reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); break; case BCM6328_CPU_ID: case BCM6338_CPU_ID: case BCM6345_CPU_ID: case BCM6358_CPU_ID: case BCM6368_CPU_ID: if (levelsense) reg |= EXTIRQ_CFG_LEVELSENSE(irq); else reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); if (sense) reg |= EXTIRQ_CFG_SENSE(irq); else reg &= ~EXTIRQ_CFG_SENSE(irq); if (bothedge) reg |= EXTIRQ_CFG_BOTHEDGE(irq); else reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); break; default: BUG(); } bcm_perf_writel(reg, regaddr); irqd_set_trigger_type(d, flow_type); if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) __irq_set_handler_locked(d->irq, handle_level_irq); else __irq_set_handler_locked(d->irq, handle_edge_irq); return IRQ_SET_MASK_OK_NOCOPY; }