void bcma_pmu_init(struct bcma_drv_cc *cc) { u32 pmucap; pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP); cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION); pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev, pmucap); if (cc->pmu.rev == 1) bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, ~BCMA_CC_PMU_CTL_NOILPONW); else bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_NOILPONW); if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2) pr_err("Fix for 4329b0 bad LPOM state not implemented!\n"); bcma_pmu_pll_init(cc); bcma_pmu_resources_init(cc); bcma_pmu_swreg_init(cc); bcma_pmu_workarounds(cc); }
static void bcma_gpio_irq_exit(struct bcma_drv_cc *cc) { if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC) return; bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO); free_irq(bcma_core_irq(cc->core, 0), cc); }
static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc) { struct gpio_chip *chip = &cc->gpio; int gpio; if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC) return; bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO); free_irq(bcma_core_irq(cc->core, 0), cc); for (gpio = 0; gpio < chip->ngpio; gpio++) { int irq = irq_find_mapping(cc->irq_domain, gpio); irq_dispose_mapping(irq); } irq_domain_remove(cc->irq_domain); }
int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n) { struct nand_chip *nand_chip = (struct nand_chip *)&b47n->nand_chip; int err; u32 freq; u16 clock; u8 w0, w1, w2, w3, w4; unsigned long chipsize; /* MiB */ u8 tbits, col_bits, col_size, row_bits, row_bsize; u32 val; nand_chip->legacy.select_chip = bcm47xxnflash_ops_bcm4706_select_chip; nand_chip->legacy.cmd_ctrl = bcm47xxnflash_ops_bcm4706_cmd_ctrl; nand_chip->legacy.dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready; b47n->nand_chip.legacy.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc; b47n->nand_chip.legacy.read_byte = bcm47xxnflash_ops_bcm4706_read_byte; b47n->nand_chip.legacy.read_buf = bcm47xxnflash_ops_bcm4706_read_buf; b47n->nand_chip.legacy.write_buf = bcm47xxnflash_ops_bcm4706_write_buf; b47n->nand_chip.legacy.set_features = nand_get_set_features_notsupp; b47n->nand_chip.legacy.get_features = nand_get_set_features_notsupp; nand_chip->legacy.chip_delay = 50; b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH; b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */ /* Enable NAND flash access */ bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG, BCMA_CC_4706_FLASHSCFG_NF1); /* Configure wait counters */ if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) { /* 400 MHz */ freq = 400000000 / 4; } else { freq = bcma_chipco_pll_read(b47n->cc, 4); freq = (freq & 0xFFF) >> 3; /* Fixed reference clock 25 MHz and m = 2 */ freq = (freq * 25000000 / 2) / 4; } clock = freq / 1000000; w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock); w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock); w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock); w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock); w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock); bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0, (w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0)); /* Scan NAND */ err = nand_scan(&b47n->nand_chip, 1); if (err) { pr_err("Could not scan NAND flash: %d\n", err); goto exit; } /* Configure FLASH */ chipsize = b47n->nand_chip.chipsize >> 20; tbits = ffs(chipsize); /* find first bit set */ if (!tbits || tbits != fls(chipsize)) { pr_err("Invalid flash size: 0x%lX\n", chipsize); err = -ENOTSUPP; goto exit; } tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */ col_bits = b47n->nand_chip.page_shift + 1; col_size = (col_bits + 7) / 8; row_bits = tbits - col_bits + 1; row_bsize = (row_bits + 7) / 8; val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2; bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val); exit: if (err) bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG, ~BCMA_CC_4706_FLASHSCFG_NF1); return err; }