/* initialize the sdio core */
void
si_sdio_init(si_t *sih)
{
	si_info_t *sii = SI_INFO(sih);

	if (((sih->buscoretype == PCMCIA_CORE_ID) && (sih->buscorerev >= 8)) ||
	    (sih->buscoretype == SDIOD_CORE_ID)) {
		uint idx;
		sdpcmd_regs_t *sdpregs;

		/* get the current core index */
		idx = sii->curidx;
		ASSERT(idx == si_findcoreidx(sih, D11_CORE_ID, 0));

		/* switch to sdio core */
		if (!(sdpregs = (sdpcmd_regs_t *)si_setcore(sih, PCMCIA_CORE_ID, 0)))
			sdpregs = (sdpcmd_regs_t *)si_setcore(sih, SDIOD_CORE_ID, 0);
		ASSERT(sdpregs);

		SI_MSG(("si_sdio_init: For PCMCIA/SDIO Corerev %d, enable ints from core %d "
		        "through SD core %d (%p)\n",
		        sih->buscorerev, idx, sii->curidx, sdpregs));

		/* enable backplane error and core interrupts */
		W_REG(sii->osh, &sdpregs->hostintmask, I_SBINT);
		W_REG(sii->osh, &sdpregs->sbintmask, (I_SB_SERR | I_SB_RESPERR | (1 << idx)));

		/* switch back to previous core */
		si_setcoreidx(sih, idx);
	}

	/* enable interrupts */
	bcmsdh_intr_enable(sii->sdh);

}
Exemple #2
0
BOOLEAN
shared_interrupt_synchronize(PNDIS_MINIPORT_INTERRUPT pintr,
	shared_info_t *sh,
	void (*SyncFunc)(void *),
	void *SyncCxt)
{
	if (sh->BusType == NdisInterfacePci || sh->BusType == NdisInterfacePcMcia) {
		return NdisMSynchronizeWithInterrupt(pintr, (void*)SyncFunc, (void*)SyncCxt);
	}
	else if (sh->BusType == NdisInterfaceSDIO) {

		{
			BOOLEAN intr_on;
			/* disable intr and reenable after reset if intr was on */
			intr_on = bcmsdh_intr_query(sh->sdh);
			if (intr_on)
				bcmsdh_intr_disable(sh->sdh);
			(SyncFunc)(SyncCxt);
			if (intr_on)
				bcmsdh_intr_enable(sh->sdh);
		}
	}
	return TRUE;
}