static void ipi_flush_icache(void *info) { struct blackfin_flush_data *fdata = info; /* Invalidate the memory holding the bounds of the flushed region. */ blackfin_dcache_invalidate_range((unsigned long)fdata, (unsigned long)fdata + sizeof(*fdata)); blackfin_icache_flush_range(fdata->start, fdata->end); }
SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, len, int, op) { if (is_user_addr_valid(current, addr, len) != 0) return -EINVAL; if (op & DCACHE) blackfin_dcache_flush_range(addr, addr + len); if (op & ICACHE) blackfin_icache_flush_range(addr, addr + len); return 0; }
void flush_cache(unsigned long addr, unsigned long size) { /* no need to flush stuff in on chip memory (L1/L2/etc...) */ if (addr >= 0xE0000000) return; if (icache_status()) blackfin_icache_flush_range((void *)addr, (void *)(addr + size)); if (dcache_status()) blackfin_dcache_flush_range((void *)addr, (void *)(addr + size)); }
void flush_cache(unsigned long dummy1, unsigned long dummy2) { if ((dummy1 >= L1_ISRAM) && (dummy1 < L1_ISRAM_END)) return; if ((dummy1 >= DATA_BANKA_SRAM) && (dummy1 < DATA_BANKA_SRAM_END)) return; if ((dummy1 >= DATA_BANKB_SRAM) && (dummy1 < DATA_BANKB_SRAM_END)) return; if (icache_status()) blackfin_icache_flush_range((void*)dummy1, (void*)(dummy1 + dummy2)); if (dcache_status()) blackfin_dcache_flush_range((void*)dummy1, (void*)(dummy1 + dummy2)); return; }
static void ipi_flush_icache(void *info) { struct blackfin_flush_data *fdata = info; /* Invalidate the memory holding the bounds of the flushed region. */ blackfin_dcache_invalidate_range((unsigned long)fdata, (unsigned long)fdata + sizeof(*fdata)); /* Make sure all write buffers in the data side of the core * are flushed before trying to invalidate the icache. This * needs to be after the data flush and before the icache * flush so that the SSYNC does the right thing in preventing * the instruction prefetcher from hitting things in cached * memory at the wrong time -- it runs much further ahead than * the pipeline. */ SSYNC(); /* ipi_flaush_icache is invoked by generic flush_icache_range, * so call blackfin arch icache flush directly here. */ blackfin_icache_flush_range(fdata->start, fdata->end); }