void board_init_f(ulong dummy) { /* Set global data pointer */ gd = &gdata; /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); #ifdef CONFIG_LS2085A arch_cpu_init(); #endif #ifdef CONFIG_FSL_IFC init_early_memctl_regs(); #endif board_early_init_f(); timer_init(); #ifdef CONFIG_LS2085A env_init(); #endif get_clocks(); preloader_console_init(); #ifdef CONFIG_SPL_I2C_SUPPORT i2c_init_all(); #endif dram_init(); /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start); #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; /* * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot * initializes DMA very early (before all board code), so the only * opportunity we have to initialize APBHDMA clocks is in SPL. */ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); enable_usdhc_clk(1, 2); arch_cpu_init(); timer_init(); cm_fx6_setup_ecspi(); cm_fx6_setup_uart(); get_clocks(); preloader_console_init(); gpio_direction_output(CM_FX6_GREEN_LED, 1); if (cm_fx6_spl_dram_init()) { puts("!!!ERROR!!! DRAM detection failed!!!\n"); hang(); } memset(__bss_start, 0, __bss_end - __bss_start); board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ arch_cpu_init(); ccgr_init(); gpr_init(); /* iomux and setup of i2c */ board_early_init_f(); /* setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); #ifndef CONFIG_TDX_APALIS_IMX6_V1_0 /* Make sure we use dte mode */ setup_dtemode_uart(); #endif /* DDR initialization */ spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { #ifdef CONFIG_CMD_NAND /* Enable NAND */ setup_gpmi_nand(); #endif /* setup clock gating */ ccgr_init(); /* setup AIPS and disable watchdog */ arch_cpu_init(); /* setup AXI */ gpr_init(); board_early_init_f(); /* setup GP timer */ timer_init(); setup_spi(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* DDR initialization */ spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { ccgr_init(); /* setup AIPS and disable watchdog */ arch_cpu_init(); /* iomux and setup of i2c */ board_early_init_f(); /* setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* DDR initialization */ spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { /* Set global data pointer */ gd = &gdata; /* Linux expects the internal registers to be at 0xf1000000 */ arch_cpu_init(); /* * Pin muxing needs to be done before UART output, since * on A38x the UART pins need some re-muxing for output * to work. */ board_early_init_f(); preloader_console_init(); timer_init(); /* First init the serdes PHY's */ serdes_phy_config(); /* Setup DDR */ ddr3_init(); board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { switch_to_main_crystal_osc(); /* disable watchdog */ at91_disable_wdt(); /* PMC configuration */ at91_pmc_init(); at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); matrix_init(); redirect_int_from_saic_to_aic(); timer_init(); board_early_init_f(); preloader_console_init(); mem_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { ccgr_init(); arch_cpu_init(); gpr_init(); /* setup GP timer */ timer_init(); displ5_set_iomux_uart_spl(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); displ5_init_ecspi(); /* DDR initialization */ spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); displ5_set_iomux_misc_spl(); /* Initialize and reset WDT in SPL */ hw_watchdog_init(); WATCHDOG_RESET(); /* load/boot image from boot device */ board_init_r(NULL, 0); }
void after_reloc (ulong dest_addr) { /* * Jump to the main U-Boot board init code */ board_init_r ((gd_t *) gd, dest_addr); /* NOTREACHED */ }
/* * This section requires the differentiation between iMX6 Sabre boards, but * for now, it will configure only for the mx6q variant. */ static void spl_dram_init(void) { struct mx6_ddr_sysinfo sysinfo = { /* width of data bus:0=16,1=32,2=64 */ .dsize = 2, /* config for full 4GB range so that get_mem_size() works */ .cs_density = 32, /* 32Gb per CS */ /* single chip select */ .ncs = 1, .cs1_mirror = 0, .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ .walat = 1, /* Write additional latency */ .ralat = 5, /* Read additional latency */ .mif3_mode = 3, /* Command prediction working mode */ .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, .refsel = 1, /* Refresh cycles at 32KHz */ .refr = 7, /* 8 refresh commands per refresh cycle */ }; if (is_mx6dqp()) { mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr); } else { mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); } } void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ arch_cpu_init(); ccgr_init(); gpr_init(); /* iomux and setup of i2c */ board_early_init_f(); /* setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* DDR initialization */ spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { /* Set global data pointer */ gd = &gdata; /* Setup global info */ #ifndef CONFIG_CMD_BURN gd->arch.gi = &ginfo; #else gd->arch.gi = (struct global_info *)CONFIG_SPL_GINFO_BASE; #endif gpio_init(); #ifndef CONFIG_FPGA /* Init uart first */ enable_uart_clk(); #endif #ifdef CONFIG_SPL_SERIAL_SUPPORT preloader_console_init(); #endif #ifndef CONFIG_FPGA debug("Timer init\n"); timer_init(); #ifdef CONFIG_SPL_REGULATOR_SUPPORT debug("regulator set\n"); spl_regulator_set(); #endif debug("CLK stop\n"); clk_prepare(); debug("PLL init\n"); pll_init(); debug("CLK init\n"); clk_init(); #endif debug("SDRAM init\n"); sdram_init(); debug("SDRAM init ok\n"); #ifdef CONFIG_DDR_TEST ddr_basic_tests(); #endif #ifndef CONFIG_BURNER /* Clear the BSS */ memset(__bss_start, 0, (char *)&__bss_end - __bss_start); debug("board_init_r\n"); board_init_r(NULL, 0); #endif }
/* * In the context of SPL, board_init_f must ensure that any clocks/etc for * DDR are enabled, ensure that the stack pointer is valid, clear the BSS * and call board_init_r. We provide this version by default but mark it * as __weak to allow for platforms to do this in their own way if needed. */ void __weak board_init_f(ulong dummy) { /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - (ulong)__bss_start); /* Set global data pointer. */ gd = &gdata; board_init_r(NULL, 0); }
void board_init_f(ulong bootflag) { init_fnc_t **init_fnc_ptr; uchar *mem; unsigned long addr_sp, addr, size; gd = &gd_mem; assert(gd); memset((void *)gd, 0, sizeof(gd_t)); #if defined(CONFIG_OF_EMBED) /* Get a pointer to the FDT */ gd->fdt_blob = _binary_dt_dtb_start; #elif defined(CONFIG_OF_SEPARATE) /* FDT is at end of image */ gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE); #endif for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) hang(); } size = CONFIG_SYS_SDRAM_SIZE; mem = os_malloc(CONFIG_SYS_SDRAM_SIZE); assert(mem); gd->ram_buf = mem; addr = (ulong)(mem + size); /* * reserve memory for malloc() arena */ addr_sp = addr - TOTAL_MALLOC_LEN; debug("Reserving %dk for malloc() at: %08lx\n", TOTAL_MALLOC_LEN >> 10, addr_sp); /* * (permanently) allocate a Board Info struct * and a permanent copy of the "global" data */ addr_sp -= sizeof(bd_t); gd->bd = (bd_t *) addr_sp; debug("Reserving %zu Bytes for Board Info at: %08lx\n", sizeof(bd_t), addr_sp); /* Ram ist board specific, so move it to board code ... */ dram_init_banksize(); display_dram_config(); /* and display it */ /* We don't relocate, so just run the post-relocation code */ board_init_r(NULL, 0); /* NOTREACHED - no way out of command loop except booting */ }
void board_init_f(ulong dummy) { ps7_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); preloader_console_init(); arch_cpu_init(); board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; unsigned int major; #ifdef CONFIG_NAND_BOOT struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; u32 porsr1, pinctl; /* * There is LS1 SoC issue where NOR, FPGA are inaccessible during * NAND boot because IFC signals > IFC_AD7 are not enabled. * This workaround changes RCW source to make all signals enabled. */ porsr1 = in_be32(&gur->porsr1); pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | DCFG_CCSR_PORSR1_RCW_SRC_I2C); out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), pinctl); #endif /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start); #ifdef CONFIG_FSL_IFC init_early_memctl_regs(); #endif get_clocks(); #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) fsl_dp_disable_console(); #endif preloader_console_init(); #ifdef CONFIG_SPL_I2C_SUPPORT i2c_init_all(); #endif major = get_soc_major_rev(); if (major == SOC_MAJOR_VER_1_0) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); dram_init(); /* Allow OCRAM access permission as R/W */ #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { arch_cpu_init(); gpr_init(); board_early_init_f(); timer_init(); preloader_console_init(); ddr_init(); memset(__bss_start, 0, __bss_end - __bss_start); board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { #if 0 arch_cpu_init(); board_early_init_f(); timer_init(); preloader_console_init(); print_cpuinfo(); board_init_r(NULL, 0); #endif }
/* * called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM * - no variable global data is available */ void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ arch_cpu_init(); ccgr_init(); gpr_init(); /* setup GP timer */ timer_init(); #ifdef CONFIG_BOARD_POSTCLK_INIT board_postclk_init(); #endif #ifdef CONFIG_FSL_ESDHC get_clocks(); #endif /* Setup IOMUX and configure basics. */ novena_spl_setup_iomux_audio(); novena_spl_setup_iomux_buttons(); novena_spl_setup_iomux_enet(); novena_spl_setup_iomux_fpga(); novena_spl_setup_iomux_i2c(); novena_spl_setup_iomux_pcie(); novena_spl_setup_iomux_sdhc(); novena_spl_setup_iomux_spi(); novena_spl_setup_iomux_uart(); novena_spl_setup_iomux_video(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* Start the DDR DRAM */ novena_read_spd(&novena_ddr_info, &novena_ddr3_cfg); mx6dq_dram_iocfg(novena_ddr3_cfg.width, &novena_ddr_ioregs, &novena_grp_ioregs); mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &novena_ddr3_cfg); do_write_level_calibration(); do_dqs_calibration(); printf("Running post-config memory test... "); if (novena_memory_test()) printf("Fail!\n"); else printf("Pass\n"); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
void board_init_f(ulong flags) { int ret; ret = x86_tpl_init(); if (ret) { debug("Error %d\n", ret); hang(); } /* Uninit CAR and jump to board_init_f_r() */ board_init_r(gd, 0); }
void board_init_f(ulong dummy) { ps7_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* Set global data pointer. */ gd = &gdata; preloader_console_init(); arch_cpu_init(); board_init_r(NULL, 0); }
/* * SPL version of board_init_f() */ void board_init_f(ulong bootflag) { end_align = (u32)__spl_flash_end; /* * On MPC5200, the initial RAM (and gd) is located in the internal * SRAM. So we can actually call the preloader console init code * before calling dram_init(). This makes serial output (printf) * available very early, even before SDRAM init, which has been * an U-Boot priciple from day 1. */ /* * Init global_data pointer. Has to be done before calling * get_clocks(), as it stores some clock values into gd needed * later on in the serial driver. */ /* Pointer is writable since we allocated a register for it */ gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset((void *)gd, 0, sizeof(gd_t)); /* * get_clocks() needs to be called so that the serial driver * works correctly */ get_clocks(); /* * Do rudimental console / serial setup */ preloader_console_init(); /* * First we need to initialize the SDRAM, so that the real * U-Boot or the OS (Linux) can be loaded */ dram_init(); /* Clear bss */ memset(__bss_start, '\0', __bss_end - __bss_start); /* * Call board_init_r() (SPL framework version) to load and boot * real U-Boot or OS */ board_init_r(NULL, 0); /* Does not return!!! */ }
/* * called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM * - no variable global data is available */ void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ arch_cpu_init(); ccgr_init(); gpr_init(); /* setup GP timer */ timer_init(); #ifdef CONFIG_BOARD_POSTCLK_INIT board_postclk_init(); #endif #ifdef CONFIG_FSL_ESDHC get_clocks(); #endif /* Setup IOMUX and configure basics. */ novena_spl_setup_iomux_audio(); novena_spl_setup_iomux_buttons(); novena_spl_setup_iomux_enet(); novena_spl_setup_iomux_fpga(); novena_spl_setup_iomux_i2c(); novena_spl_setup_iomux_pcie(); novena_spl_setup_iomux_sdhc(); novena_spl_setup_iomux_spi(); novena_spl_setup_iomux_uart(); novena_spl_setup_iomux_video(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* Start the DDR DRAM */ mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs); mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600); /* Perform DDR DRAM calibration */ udelay(100); mmdc_do_write_level_calibration(); mmdc_do_dqs_calibration(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { psu_init(); board_early_init_r(); #ifdef CONFIG_DEBUG_UART /* Uart debug for sure */ debug_uart_init(); puts("Debug uart enabled\n"); /* or printch() */ #endif /* Delay is required for clocks to be propagated */ udelay(1000000); /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start); /* No need to call timer init - it is empty for ZynqMP */ board_init_r(NULL, 0); }
int main(int argc, char *argv[]) { struct sandbox_state *state; gd_t data; int ret; ret = state_init(); if (ret) goto err; state = state_get_current(); if (os_parse_args(state, argc, argv)) return 1; ret = sandbox_read_state(state, state->state_fname); if (ret) goto err; /* Remove old memory file if required */ if (state->ram_buf_rm && state->ram_buf_fname) os_unlink(state->ram_buf_fname); memset(&data, '\0', sizeof(data)); gd = &data; #if CONFIG_VAL(SYS_MALLOC_F_LEN) gd->malloc_base = CONFIG_MALLOC_F_ADDR; #endif setup_ram_buf(state); /* Do pre- and post-relocation init */ board_init_f(0); board_init_r(gd->new_gd, 0); /* NOTREACHED - board_init_r() does not return */ return 0; err: printf("Error %d\n", ret); return 1; }
/* * SPL version of board_init_f() */ void board_init_f(ulong bootflag) { /* * First we need to initialize the SDRAM, so that the real * U-Boot or the OS (Linux) can be loaded */ initdram(0); /* Clear bss */ memset(__bss_start, '\0', __bss_end - __bss_start); /* * Init global_data pointer. Has to be done before calling * get_clocks(), as it stores some clock values into gd needed * later on in the serial driver. */ /* Pointer is writable since we allocated a register for it */ gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset((void *)gd, 0, sizeof(gd_t)); /* * get_clocks() needs to be called so that the serial driver * works correctly */ get_clocks(); /* * Do rudimental console / serial setup */ preloader_console_init(); /* * Call board_init_r() (SPL framework version) to load and boot * real U-Boot or OS */ board_init_r(NULL, 0); /* Does not return!!! */ }
void board_init_f(ulong dummy) { int ret; /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); arch_cpu_init(); init_uart_clk(0); board_early_init_f(); timer_init(); preloader_console_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); ret = spl_init(); if (ret) { debug("spl_init() failed: %d\n", ret); hang(); } enable_tzc380(); /* Adjust pmic voltage to 1.0V for 800M */ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); power_init_board(); /* DDR initialization */ spl_dram_init(); board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { void (*second_uboot)(void); /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start); get_clocks(); #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) fsl_dp_disable_console(); #endif preloader_console_init(); dram_init(); /* Allow OCRAM access permission as R/W */ #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); enable_layerscape_ns_access(); #endif /* * if it is woken up from deep sleep, then jump to second * stage uboot and continue executing without recopying * it from SD since it has already been reserved in memeory * in last boot. */ if (is_warm_boot()) { second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE; second_uboot(); } board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ arch_cpu_init(); ccgr_init(); gpr_init(); /* setup GP timer */ timer_init(); setup_iomux_boardid(); setup_iomux_gpio(); setup_iomux_enet(); setup_iomux_sd(); setup_iomux_spi(); setup_iomux_uart(); setup_iomux_usb(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* Start the DDR DRAM */ if (is_mx6dq()) mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs, &dhcom6dq_grp_ioregs); else mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs, &dhcom6sdl_grp_ioregs); mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start); get_clocks(); #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) fsl_dp_disable_console(); #endif preloader_console_init(); dram_init(); /* Allow OCRAM access permission as R/W */ #ifdef CONFIG_LS102XA_NS_ACCESS enable_devices_ns_access(&ns_dev[4], 1); enable_devices_ns_access(&ns_dev[7], 1); #endif board_init_r(NULL, 0); }
static void spl_dram_init(int width) { struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125; struct mx6_ddr_sysinfo sysinfo = { /* width of data bus:0=16,1=32,2=64 */ .dsize = width / 32, /* config for full 4GB range so that get_mem_size() works */ .cs_density = 32, /* 32Gb per CS */ /* single chip select */ .ncs = 1, .cs1_mirror = 1, .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ #ifdef RTT_NOM_120OHM .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ #else .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ #endif .walat = 0, /* Write additional latency */ .ralat = 5, /* Read additional latency */ .mif3_mode = 3, /* Command prediction working mode */ .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, .refsel = 1, /* Refresh cycles at 32KHz */ .refr = 7, /* 8 refresh commands per refresh cycle */ }; mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); } /* * Called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM * - no variable global data is available */ void board_init_f(ulong dummy) { /* Setup AIPS and disable watchdog */ arch_cpu_init(); ccgr_init(); gpr_init(); /* UART iomux */ board_early_init_f(); /* Setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* Init DDR with 32bit width */ spl_dram_init(32); /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start); /* * Setup enet related MUXing early to give the PHY * some time to wake-up from reset */ platinum_setup_enet(); /* load/boot image from boot device */ board_init_r(NULL, 0); }