void enable_board_pin_mux(void)
{
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(mdio_pin_mux);
if (board_is_evm()) {
configure_module_pin_mux(gpio5_7_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
#if defined(CONFIG_NAND)
configure_module_pin_mux(nand_pin_mux);
#endif
} else if (board_is_sk() || board_is_idk()) {
configure_module_pin_mux(rgmii1_pin_mux);
#if defined(CONFIG_NAND)
printf("Error: NAND flash not present on this board\n");
#endif
configure_module_pin_mux(qspi_pin_mux);
} else if (board_is_eposevm()) {
configure_module_pin_mux(rmii1_pin_mux);
#if defined(CONFIG_NAND)
configure_module_pin_mux(nand_pin_mux);
#else
configure_module_pin_mux(qspi_pin_mux);
#endif
}
}
void sdram_init(void)
{
/*
* EPOS EVM has 1GB LPDDR2 connected to EMIF.
* GP EMV has 1GB DDR3 connected to EMIF
* along with VTT regulator.
*/
if (board_is_eposevm()) {
config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
} else if (board_is_evm_14_or_later()) {
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz_production, 0);
} else if (board_is_evm_12_or_later()) {
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz_beta, 0);
} else if (board_is_evm()) {
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz, 0);
} else if (board_is_sk()) {
config_ddr(400, &ioregs_ddr3, NULL, NULL,
&ddr3_sk_emif_regs_400Mhz, 0);
} else if (board_is_idk()) {
config_ddr(400, &ioregs_ddr3, NULL, NULL,
&ddr3_idk_emif_regs_400Mhz, 0);
}
}
const struct dpll_params *get_dpll_ddr_params(void)
{
if (board_is_eposevm())
return &epos_evm_dpll_ddr;
else if (board_is_gpevm() || board_is_sk())
return &gp_evm_dpll_ddr;
printf(" Board '%s' not supported\n", am43xx_board_name);
return NULL;
}
int board_fit_config_name_match(const char *name)
{
if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
return 0;
else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
return 0;
else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
return 0;
else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
return 0;
else
return -1;
}
const struct dpll_params *get_dpll_ddr_params(void)
{
int ind = get_sys_clk_index();
if (board_is_eposevm())
return &epos_evm_dpll_ddr[ind];
else if (board_is_evm() || board_is_sk())
return &gp_evm_dpll_ddr;
else if (board_is_idk())
return &idk_dpll_ddr;
printf(" Board '%s' not supported\n", board_ti_get_name());
return NULL;
}
u32 rtc_only_get_board_type(void)
{
if (board_is_eposevm())
return RTC_BOARD_EPOS;
else if (board_is_evm_14_or_later())
return RTC_BOARD_EVM14;
else if (board_is_evm_12_or_later())
return RTC_BOARD_EVM12;
else if (board_is_gpevm())
return RTC_BOARD_GPEVM;
else if (board_is_sk())
return RTC_BOARD_SK;
return 0;
}
void enable_board_pin_mux(struct am335x_baseboard_id *header)
{
debug(">>pia:enable_board_pin_mux() for board %.8s\n",header->name);
if (board_is_e2(header)) {
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(mii2_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
if (0 == strncmp(header->version, "0.01", 4))
configure_module_pin_mux(e2_supervisor_pin_mux);
else
configure_module_pin_mux(e2_r2_supervisor_pin_mux);
if (0 == strncmp(header->version, "0.03", 4))
configure_module_pin_mux(e2_r3_poe_pin_mux);
init_pia_e2_gpios(header);
} else if (board_is_mmi(header)) {
configure_module_pin_mux(mmi_i2c1_pin_mux);
configure_module_pin_mux(mmi_mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(mmi_supervisor_pin_mux);
configure_module_pin_mux(mmi_pmic_pin_mux);
configure_module_pin_mux(mmi_accl_pin_mux);
configure_module_pin_mux(mmi_audio_pin_mux);
configure_module_pin_mux(lcdc_pin_mux);
init_pia_mmi_gpios();
} else if (board_is_ebtft(header)) {
configure_module_pin_mux(pia335x_pm);
configure_module_pin_mux(pia335x_eb_tft);
init_pia_ebtft_gpios();
} else if (board_is_em(header)) {
configure_module_pin_mux(lokisa_em);
init_lokisa_em_gpios();
} else if (board_is_sk(header)) {
configure_module_pin_mux(pia335x_pm);
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(pia335x_sk);
init_sk_gpios();
} else if (board_is_dr(header)) {
configure_module_pin_mux(pia335x_pm);
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(pia335x_dr);
init_dr_gpios();
} else if (board_is_pia(header)) {
configure_module_pin_mux(pia335x_pm);
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(pia3352_pin_mux);
init_pia_gpios();
}
}
int board_fit_config_name_match(const char *name)
{
bool eeprom_read = board_ti_was_eeprom_read();
if (!strcmp(name, "am4372-generic") && !eeprom_read)
return 0;
else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
return 0;
else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
return 0;
else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
return 0;
else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
return 0;
else
return -1;
}
void enable_board_pin_mux(void)
{
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(mdio_pin_mux);
if (board_is_gpevm()) {
configure_module_pin_mux(gpio5_7_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
} else if (board_is_sk()) {
configure_module_pin_mux(rgmii1_pin_mux);
configure_module_pin_mux(qspi_pin_mux);
} else if (board_is_eposevm()) {
configure_module_pin_mux(rmii1_pin_mux);
configure_module_pin_mux(qspi_pin_mux);
}
}
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
{
if (board_is_eposevm()) {
*regs = ext_phy_ctrl_const_base_lpddr2;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
} else if (board_is_evm_14_or_later()) {
*regs = ext_phy_ctrl_const_base_ddr3_production;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production);
} else if (board_is_evm_12_or_later()) {
*regs = ext_phy_ctrl_const_base_ddr3_beta;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta);
} else if (board_is_gpevm()) {
*regs = ext_phy_ctrl_const_base_ddr3;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
} else if (board_is_sk()) {
*regs = ext_phy_ctrl_const_base_ddr3_sk;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
}
return;
}
int board_eth_init(bd_t *bis)
{
int rv;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (!env_get("ethaddr")) {
puts("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
}
mac_lo = readl(&cdev->macid1l);
mac_hi = readl(&cdev->macid1h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (!env_get("eth1addr")) {
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("eth1addr", mac_addr);
}
if (board_is_eposevm()) {
writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
cpsw_slaves[0].phy_addr = 16;
} else if (board_is_sk()) {
writel(RGMII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
cpsw_slaves[0].phy_addr = 4;
cpsw_slaves[1].phy_addr = 5;
} else if (board_is_idk()) {
writel(RGMII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
cpsw_slaves[0].phy_addr = 0;
} else {
writel(RGMII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
cpsw_slaves[0].phy_addr = 0;
}
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
return rv;
}
